FlexSPI A2 Chip Select Not Toggling

[chadgraham]

Hello,

For the last 2 weeks, I've struggled to add a second QSPI chip to a RT1060EVK dev board.  I have posted numerous forum questions and I don't know what the issue is.  The app note AN12564, while useful, doesn't actually show you how to modify the code to make the second chip work and the reference manual has a lot of detail, but doesn't explain what needs to happen in code.

On the dev board, we have hooked up a second QSPI device to FlexSPI A.  The device is identical to the one already on the board and we set FLEXSPI_A_SS1_B to [H13] GPIO_AD_B1_08.

In software, we are trying to modify the "evkmimxrt1060_flexspi_nor_polling_transfer" project.  In the project settings, we added the second flash as "Flash_00" and assigned it to 0x60800000 and a size of 0x800000.  We have updated the pin_mux files and added the ".sflashA2Size" command to "xip\evkmimxrt1060_flexspi_nor_config.c".  In app.h, the FLASH_SIZE was increased from 0x2000 to 0x4000 and in the project, we modified the flex_spi_flash_init() command to include "FLEXSPI_SetFlashConfig(base, &deviceconfig, kFLEXSPI_PortA2)"

Looking at the memory viewer, I can see that the memory location 0x60800000 seems to contain memory configuration data, but starting at location 0x60802000 I can see the actual A1 program data.  Additionally, the A2 chip select signal is not toggling when I try reading the A2 memory locations which tells me that I have a setup issue.

Numerous Questions:

1. Given the example, does anyone see any issues with the demo?
2. What needs to happen to specifically assign SS1 to be used by the internal memory controller?
3. If we have the same exact chip, do I need to update the LUT?  (It looks like there is only a single LUT for all chips so we shouldn't need to update it.)
4. We plan to use the second memory chip as a XIP memory location that gets called by a bootloader.  Looking at the reference manual, app notes and other forum posts, it looks like I do not want to set the chips up as parallel.  Is that correct?
5. Looking in the reference manual, and other posts, it seems like I should be able to have both devices on the same FlexSPI bus.  However, one suggestion would be to move the second chip to FlexSPI B.  Is that necessary?  (It would be a big problem since the final design has provisioned these pins to other signals.)
6. One thought was that I might need to update "MIMXRT1060_SFDP_QSPI.cfx", but I cannot locate the source code and working with the RT1050 example did not prove helpful.  Do I need to continue pursuing the source code so I can modify it or is that not going to help?

[stefanct]

One important detail that is not even remotely touched in the datasheet (RT1021 in my case) or SDK docs is how the FLEXSPI IP determines the CS pin to use in explicit transfers (i.e., via FLEXSPI_Transfer* functions where a flexspi_transfer_t is involved). Since there is a `port` field in flexspi_transfer_t one would assume that this is used by the hardware to determine the pin. However, that is not the case - presumably because that information is not available for memory-mapped transfers - but it uses the deviceAddress field. And said field is not the equivalent of the memory-mapped AHB/AMBA address but the memory-mapped address without the FLEXSPI AHB offset (FlexSPI_AMBA_BASE)!

The FLEXSPI address space is laid out according to the flashSize in flexspi_device_config_t passed to FLEXSPI_SetFlashConfig() (which determine the FLSHSZ fields of FLSH*CR0) sequentially in port order (AFAICT).

Figuring this out was a great experience.

[jingpan]

Hi @chadgraham ,

But in your code, when calling flexspi_nor_flash_erase_sector() and flexspi_nor_flash_page_program(), it still erase/write kFLEXSPI_PortA1, not kFLEXSPI_PortA2. So, I'm not clearly get what you want. I modified your code, change all A1 to A2 in flexspi_nor_fklash_ops.c, and change EXAMPLE_FLEXSPI_AMBA_BASE definition to 0x60800000. It works well. I can see the right data in 0x60814000.

Can AN12564sw run on your board?

Regards,

Jing

[chadgraham]

Hello Jing,

Thank you for your input.

1. Based on my understanding, changing EXAMPLE_FLEXSPI_AMBA_BASE changes the base address of the first FlexSpi device, but doesn't allow access to the second device.  (EXAMPLE_FLEXSPI_AMBA_BASE + 0x80 0000)
2. Specifically, I'm looking for the ability to confirm that the second chip select (SS1) is properly setup.  If I watch the signal going to the second QSPI it never toggles, even when it is to be accessed.  (I believe that using the memory viewer should toggle the chip select with the proper address range.  Just in case that wasn't working, I had also modified the "flexspi_nor_get_vendor_id()" function to specifically access kFLEXSPI_PortA2.)
3. If I watch the console log during programming, the flash driver is recongnizing 2 devices on the FlexSPI, both at location 0x6000 0000.  Looking closely at the memory viewer, the data starting at 0x6000 0000 and the data starting at 0x6080 0000 are identical.  This, to me, implies that the chip is accessing the memory, but utilizing the wrong chip select.  Is it possible that "MIMXRT1060_SFDP_QSPI.cfx" is preventing me from setting up the FlexSPI port?  Do I need to update "MIMXRT1060_SFDP_QSPI.cfx"?

[jingpan]

Hi,

This is my code. Please take a look.

If you don't change the base address, memcpy will still access flash A1.

memcpy(s_nor_read_buffer, (void *)(EXAMPLE_FLEXSPI_AMBA_BASE + EXAMPLE_SECTOR * SECTOR_SIZE), sizeof(s_nor_read_buffer));

Regards,

Jing

[chadgraham · Accepted solution]

Hello Jing,

Thank you for your project.  It still didn't work for me, but I was able to use it to locate my problem.  (A combination of the wrong device address and the pin setup.)  In case anyone else has the same issue, I'm attaching the version of my example project that I was able to get working.

For people trying to replicate this, the SS1 chip select is routed to J22.4.