Debugging IS25LP064A on MIMXRT1050-EVK

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Debugging IS25LP064A on MIMXRT1050-EVK

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Contributor III

Hi,

I changed the QSPI IC from the IS25WP064A to the IS25LP064A part and swaped the resistor on R49 with R301 to supply it with 3.3v. The IS25LP064A part is the 3.3v version.

There is a driver supplied with MCUXpresso for LPC-Link2 for this IC but it doesn't seem to work (MIMXRT1020-EVK_IS25LP064.cfx).  Has anyone managed to successfully get this working?

Output attached, I also tried the MIMXRT1020-EVK_IS25WP064.cfx driver which got further along to the actually programming phase before it failed.

A J-Link debugger works with the same configuration so it doesn't seem to be an issue with the PCB.

Advice?  I think there could be a bug in the MIMXRT1020-EVK_IS25LP064.cfx driver..?

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NXP Employee
NXP Employee

Have you tried using the "RT1050_Debug_Connect.scp" script provided with and described in the blog article?

How are you powering your board?

And are you using the "original" RT1050 EVK or the EVKB ? (background info at i.MX RT1050 EVK vs. EVKB | MCU on Eclipse )

Regards,

MCUXpresso IDE Support

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NXP Employee
NXP Employee

First of all power your board and probe off and on again before making any more attempts to debug. We've noticed that external probes work more reliably if you turn the board on before the probe is powered up.

Also before making another attempt to debug, make sure that all debug related tasks have closed down cleanly, using the "Clean up debug" button on the main tool bar.

Make sure that JP2 is fitted on your LPC-Link2 : we've noticed that these boards don't seem to provide the VTREF back to LPC-Link2 reliably (see Design Considerations for Debug ).

Also remove the jumpers J32 and J33 on your RT board and provide external power - with J1 jumpered appropriately.

Finally please note, that we have issued an updated version of our doc on using MCUXpresso IDE with the RT1050 board towards the end of last week. So even if you have looked at this previously, it might be worth having another look through: 

Regards,

MCUXpresso IDE Support

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Contributor III

I can debug a RAM based project just fine with the LPC-Link2.  It is only when try to debug using XIP external flash it does not work.  This would indicate the connection between the core and the LPC-Link2 is correct?

I have followed the guides you suggested.  All jumpers are set correctly.

MCUXpresso IDE RedlinkMulti Driver v10.2 (Jul 25 2018 11:25:37 - crt_emu_cm_redlink build 555)
Found chip XML file in C:/Users/smithcr/Documents/MCUXpressoIDE_10.2.1_795/workspace/evkbimxrt1050_hello_world/Debug\MIMXRT1052xxxxB.xml
Reconnected to existing link server
Connecting to probe 1 core 0:0 (using server started externally) gave 'OK'
Probe Firmware: LPC-LINK2 CMSIS-DAP V5.183 (NXP Semiconductors)
Serial Number: JQDYIRA2
VID:PID: 1FC9:0090
USB Path: \\?\hid#vid_1fc9&pid_0090&mi_00#8&da3a954&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}
Using memory from core 0:0 after searching for a good core
debug interface type = Cortex-M7 (DAP DP ID 0BD11477) over SWD TAP 0
processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0
number of h/w breakpoints = 8
number of flash patches = 0
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 0BD11477. CpuID: 00000C27. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
Content of CoreSight Debug ROM(s):
RBASE E00FD000: CID B105100D PID 000008E88C ROM dev (type 0x1)
ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM dev (type 0x1)
ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM dev (type 0x1)
ROM 3 E000E000: CID B105E00D PID 04000BB00C ChipIP dev SCS (type 0x0)
ROM 3 E0001000: CID B105E00D PID 04000BB002 ChipIP dev DWT (type 0x0)
ROM 3 E0002000: CID B105E00D PID 04000BB00E ChipIP dev (type 0x0)
ROM 3 E0000000: CID B105E00D PID 04000BB001 ChipIP dev ITM (type 0x0)
ROM 2 E0041000: CID B105900D PID 04001BB975 ARCH 23B:4A13r0 CoreSight dev type 0x13 Trace Source - core
ROM 2 E0042000: CID B105900D PID 04004BB906 CoreSight dev type 0x14 Debug Control - Trigger, e.g. ECT
ROM 1 E0040000: CID B105900D PID 04000BB9A9 CoreSight dev type 0x11 Trace Sink - TPIU
ROM 1 E0043000: CID B105F00D PID 04001BB101 System dev (type 0x0)
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT1050_SFDP_QSPI.cfx
Image 'iMXRT1050_SFDP_QSPI Jul 25 2018 11:28:10'
Opening flash driver MIMXRT1050_SFDP_QSPI.cfx
Sending VECTRESET to run flash driver
Flash variant 'JEDEC_SFDP_Device' detected (8MB = 128*64K at 0x60000000)
Closing flash driver MIMXRT1050_SFDP_QSPI.cfx
Non-standard DAP stride detected - 1024 bytes
NXP: MIMXRT1052xxxxB
Connected: was_reset=false. was_stopped=false
Awaiting telnet connection to port 3330 ...
GDB nonstop mode enabled
Opening flash driver MIMXRT1050_SFDP_QSPI.cfx (already resident)
Sending VECTRESET to run flash driver
core registers failed - rc Ep(08). Cannot access core regs when target running.
Target error from Commit Flash write: Ep(08). Cannot access core regs when target running.
GDB stub (crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB.

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NXP Employee
NXP Employee

The prebuilt driver for the RT1020 EVK board is not suitable for use on the RT1050 board (due to pinmuxing and other differences between the MCUs).

Try using the new "MIMXRT1050_SFDP_QSPI.cfx" flash driver provided in the newly released MCUXpresso IDE v10.2.1 instead.

Regards,

MCUXpresso IDE Support

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Contributor III

SDFP driver also does not work.  Output is as follows:

Connecting to probe 1 core 0:0 (using server started externally) gave 'OK'
Probe Firmware: LPC-LINK2 CMSIS-DAP V5.183 (NXP Semiconductors)
Serial Number: JQDYIRA2
VID:PID: 1FC9:0090
USB Path: \\?\hid#vid_1fc9&pid_0090&mi_00#8&da3a954&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030}
Using memory from core 0:0 after searching for a good core
debug interface type = Cortex-M7 (DAP DP ID 0BD11477) over SWD TAP 0
processor type = Cortex-M7 (CPU ID 00000C27) on DAP AP 0
number of h/w breakpoints = 8
number of flash patches = 0
number of h/w watchpoints = 4
Probe(0): Connected&Reset. DpID: 0BD11477. CpuID: 00000C27. Info: <None>
Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled.
Content of CoreSight Debug ROM(s):
RBASE E00FD000: CID B105100D PID 000008E88C ROM dev (type 0x1)
ROM 1 E00FE000: CID B105100D PID 04000BB4C8 ROM dev (type 0x1)
ROM 2 E00FF000: CID B105100D PID 04000BB4C7 ROM dev (type 0x1)
ROM 3 E000E000: CID B105E00D PID 04000BB00C ChipIP dev SCS (type 0x0)
ROM 3 E0001000: CID B105E00D PID 04000BB002 ChipIP dev DWT (type 0x0)
ROM 3 E0002000: CID B105E00D PID 04000BB00E ChipIP dev (type 0x0)
ROM 3 E0000000: CID B105E00D PID 04000BB001 ChipIP dev ITM (type 0x0)
ROM 2 E0041000: CID B105900D PID 04001BB975 ARCH 23B:4A13r0 CoreSight dev type 0x13 Trace Source - core
ROM 2 E0042000: CID B105900D PID 04004BB906 CoreSight dev type 0x14 Debug Control - Trigger, e.g. ECT
ROM 1 E0040000: CID B105900D PID 04000BB9A9 CoreSight dev type 0x11 Trace Sink - TPIU
ROM 1 E0043000: CID B105F00D PID 04001BB101 System dev (type 0x0)
Inspected v.2 External Flash Device on SPI using SFDP JEDEC ID MIMXRT1050_SFDP_QSPI.cfx
Image 'iMXRT1050_SFDP_QSPI Jul 25 2018 11:28:10'
Opening flash driver MIMXRT1050_SFDP_QSPI.cfx
Sending VECTRESET to run flash driver
Flash variant 'JEDEC_SFDP_Device' detected (8MB = 128*64K at 0x60000000)
Closing flash driver MIMXRT1050_SFDP_QSPI.cfx
Non-standard DAP stride detected - 1024 bytes
NXP: MIMXRT1052xxxxB
Connected: was_reset=false. was_stopped=false
Awaiting telnet connection to port 3331 ...
GDB nonstop mode enabled
Opening flash driver MIMXRT1050_SFDP_QSPI.cfx (already resident)
Sending VECTRESET to run flash driver
Flash variant 'JEDEC_SFDP_Device' detected (8MB = 128*64K at 0x60000000)
Writing 23160 bytes to address 0x60000000 in Flash
ProgramPage (0x60000000, 0x200057A8, 0x4000) status 0x1 - driver reported driver error - EXTSPIJ driver rc -70 (0xFFFFFFBA)
Closing flash driver MIMXRT1050_SFDP_QSPI.cfx
Target error from Commit Flash write: Ef(49): Flash driver operation gave error.

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