PLU configuration tool: Odin II does not support combinational

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PLU configuration tool: Odin II does not support combinational

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randa_zarrouk
Contributor III

I got this kind of error while importing the verilog file in the PLU configuration tool: 

 (Line number 125) you have defined this driver top^K twice.
 ERR> Note that Odin II does not currently support combinational a=?  overiding for if and case blocks.

I was trying to use If statement subsequently to an other if statement (not nested) in the second if statement block, I was using the sensibility parameter, the outputs of the previous if statement block. 

Any idea how to overcome the problem? 

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5 Replies

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randa_zarrouk
Contributor III

Hello Sabina, 

Thank you for your support.

Here is the Verilog code

module main(K,Y,B,A);

output K; 
output Y;

input A;  
input B;

reg [1:0] m;
reg [1:0] n;


always @(m[1],m[0],B, A)

begin
    case({B,A})

        2'b11 : begin
                  m[0] = 1'b0 ;
                  m[1] = 1'b1 ;
                  end

         default :
                     begin
                    m[0] = 1'b1 ;
                    m[1] = 1'b1 ;
                    end
    endcase


Y = m[0];
K = m[1];


    case ({m[1],m[0]})
              2'b11 : begin
                          n[0] = 1'b0 ;
                          n[1] = 1'b1 ;
                          end
              default :
                          begin
                          n[0] = 1'b1 ;
                          n[1] = 1'b1 ;
              end
       endcase

Y = n[0];
K = n[1];

end


endmodule

The idea is I want to assign sequentially different values to the outputs (Y and K), in the first place it gets the values from the first case block, then output gets an update from the second case block. 

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Sabina_Bruce
NXP Employee
NXP Employee

Hello Randa,

Thank you for providing further information. Based on your description I believe you will need to consider redesigning your verilog code. In this case to create a sequential block that will have a certain output in Y and K and then be updated, it will be necessary to include a clock signal in order to have these values "saved"  and then a next cycle updated. This way you will be able to use a flip flop for the memory section and consequently update values.

Please let me know if you have questions.

Best Regards,

Sabina

1,265 Views
Sabina_Bruce
NXP Employee
NXP Employee

Hello Randa,

Hope you are doing well. I would like to clarify, are you importing from Odin II to the PLU configuration tool or importing from the PLU to Odin II.

Also if you could specify what microcontroller you are using as well as the type of file you are importing.

Best Regards,

Sabina

1,265 Views
randa_zarrouk
Contributor III

Hi Sabina, 

Thank you for your response.

My target microcontroller is the LPC55S69. 

In order to generate the C code of a design using the PLU, there is several ways, one of them it to import a file written in Verilog (*.v) to the PLU configuration tool. If the file is successfully imported then next steps would be mapping the PLU inputs and outputs. In my case the file was not successfully imported, instead I got the error message above.  

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Sabina_Bruce
NXP Employee
NXP Employee

Hello Randa,

If possible could you please share your verilog file so that I may replicate this error from my side. 

Best Regards,

Sabina