Debugging programs larger than 128 KB on the MIMXRT1060-EVKB with LinkServer/CMSIS-DAP

[vascofsantos]

I am using MCUXpresso for VSCode and trying to debug an application on an MIMXRT1060-EVKB board.

Everything works fine until my program size seemingly surpasses the 128 KB size mark.

I have my linker map set to use the whole 512 KB at 0x00000000 as ITCM, so it should fit.

However, I get an error message dialog window that says:

Unable to start debugging. Unexpected GDB output from command "-interpreter-exec console "load"". Load failed

After some digging into the debug console logs, I see this:

[Warning] 1: (6334) STDERR: Wc: ============= SCRIPT: RT1060_connect.scp =============
[Warning] 1: (6334) STDERR: Wc: RT1060 Connect Script
[Warning] 1: (6334) STDERR: Wc: DpID = 0BD11477
[Warning] 1: (6334) STDERR: Wc: APID = 0x04770041
[Warning] 1: (6334) STDERR: Wc: Disabling MPU
[Warning] 1: (6334) STDERR: Wc: Configure FlexRAM for 768KB OC RAM, 128KB I-TCM, 128KB D-TCM
[Warning] 1: (6334) STDERR: Wc: Finished
[Warning] 1: (6334) STDERR: Wc: ============= END SCRIPT =============================

This RT1060_connect.scp script in the LinkServer folder seems to explicitly configure RAM with a 128 KB limit on ITCM.

This part of the script itself looks like this:

360 REM ====== Configure FlexRAM ======
370 print "Configure FlexRAM for 768KB OC RAM, 128KB I-TCM, 128KB D-TCM"
380 REM TCM CTRL Poke 0x400B0000 - to force RAM clocking and set wait states = b100
390 Poke32 this 0x400B0000 0x4
400 REM IOMUXC_GPR17 0x400AC044 - this sets bitfield allocation of FlexRAM 32KB banks to OC 256KB b01, I 128KB b11, D 128KB b10
410 Poke32 this 0x400AC044 0x5555FFAA
420 REM IOMUXC_GPR16 0x400AC040 - this sets enables for I and DTCM and the source of the TCM config = 0x200007
430 Poke32 this 0x400AC040 0x200007
440 print "Finished"
450 REM ===============================

Where can I find information on how to override/customize this FlexRAM setup into matching my linker file contents (or some other config)?

Thanks in advance!

[Gavin_Jia · Accepted solution]

Hi @vascofsantos ,

Thanks for your interest in NXP MIMXRT series!

There is a detailed guidance document on this subject which is based on the MCUXpresso IDE. The VScode based operation is currently untried. Please check this article: Reallocating the FlexRAM - NXP Community

Also this error should be reported because the connection script has not made the corresponding changes, the idea on my side is to change the register values in it:

IOMUXC_GPR17 

 Here's a new connection script based on the RT1050 that modifies the original 128-128-256 ITCM/DTCM/OCRAM to 128-256-128 ITCM/DTCM/OCRAM

It looks to me like it simply modifies the value of IOMUXC_GPR17 to 0x5AAFFAA5. So you could try something along those lines. 

100 REM===============================
110 REM RT1050_connect.scp
120 REM
130 REM Copyright 2019 NXP
140 REM All rights reserved.
150 REM===============================
160 print "RT1050 ConnectScript"
170 REM probelist
180 p% = probefirstfound
190 rem probeopenbyindex p%
200 wireswdconnect p%
210 selectprobecore p% 0
220 cminitapdp this
230 cmhalt this
235 goto 320
240 rem trap in bootrom
250 cmwatchset this 0 0x400F8004 RW
260 cmresetvectorcatchclear this
270 print "Resetting andtrapping"
280 cmsysresetreq this
290 print "Back from reset"
300 cmresetvectorcatchset this
310 cmwatchclear this 0
320 print "Disabling MPU"
330 s% = Peek32 this 0xE000ED94
340 s% = s% & 0xFFFFFFFE
350 Poke32 this 0xE000ED94 s%
360 REM ====== Configure FlexRAM======
370 print "Configure FlexRAM for128KB OC RAM, 128KB I-TCM, 256KB D-TCM"
380 REM TCM CTRL Poke 0x400B0000 - toforce RAM clocking and set wait states = b100
390 Poke32 this 0x400B0000 0x4
400 REM IOMUXC_GPR17 0x400AC044 - thissets bitfield allocation of FlexRAM 32KB banks to OC 256KB b01, I 128KB b11, D128KB b10
410 Poke32 this 0x400AC044 0x5AAFFAA5
420 REM IOMUXC_GPR16 0x400AC040 - thissets enables for I and DTCM and the source of the TCM config = 0x200007
430 Poke32 this 0x400AC040 0x200007
440 print "Finished"
450 REM===============================
460 end

Best regards,
Gavin

[vascofsantos]

I confirm that this method works in VSCode.

Thank you @Gavin_Jia!