LPC54113 CLK Generation

[andreasruetten]

Hello,

i want to use an 10Mhz external clock from an Oszillator.

System clock shall be 120Mhz.

( by the way the data sheet says up to 150Mhz , manual UM10914 says 100Mhz )

I want to feed the flexcoms with the pll and not with the fro.

But i can't use the tool for that.

FRGCLKSEL to pll_clk will lead to the only option *256, which in my opinion is nonsense!

Error Message :

Issue: Output frequency must be lower than or equal to: 48 MHz
Level: Error
Type: Tool problem
Tool: Clocks
Origin: Clocks: BOARD_BootClockRUN
Resource: SYSCON.FRGCTRL_DIV
Information: Output frequency must be lower than or equal to: 48 MHz (See constraint 1)

[ZhangJennie]

Hi andreasruetten,

According to UM10914

"The Flexcomm Interface function clock frequency should not be higher than 48 MHz."

That's why we can't set Flexcom clock higher than 48Mhz in Configuration tool.

Thanks,

Jun Zhang

[andreasruetten]

Hi,

i don't want to set the freqency of the Flexcom clock  higher than 48Mhz,

that was not my question!

I have an external 20Mhz input and 120Mhz Pll clock.

Please take a look on the picture i send!

My problem is the fixed *256 multiplicator in the tool.

Thanks Andreas

[marek_neuzil]

Hello Andreas,

Let me explain the problem of the fractional divider of the LPC5411x MCU. The description of the functionality is little bit confusing in the user manual UM10914. You can find the following description of the FRGCTRL and also the functional description of Flexcomm fractional rate divider:

As you can see, when you transform the expression, there is fixed multiplicator 256 and divider with range 256 - 511. This is the functionality that is provided in this MCU.

I have checked the possibilities of the Flexcomm fractional divider and System PLL. If you need both the PLL output and main_clk to be 120 MHz the fractional divider cannot be used to divide the 120 MHz to 48 MHz (or lower). This combination of setting is not support on this MCU.

If you just need the PLL output 120 MHz and main_clk can use different clock source (for example the external clock source 20 MHz) the FRGCLKSEL can be use to select the main_clk and the fractional divider can be set to provide a requested frequency for the FLEXCOMM peripheral.

Best Regards,

Marek Neuzil

[andreasruetten]

Hi Marek,

that does mean, that there is no possibility to power the core with 120Mhz and 

an accuracy better than 1% ( with external source ) on flexcom interfaces ?

Our problem is that we need the processor power at high speed and accuracy better then 1%

Andreas

[marek_neuzil]

Hi Andreas,

In this case you can also use the MCLKIN input (mclk_in clock source) for the Flexcomm interface. You can use for example the same external reference clock 20 MHz as it is used for the clk_in.

The mclk_in reference clock can be selected in FXCOMCLKSEL0 clock selector.

Best Regards,

Marek Neuzil

[andreasruetten]

Hi Marek,

Data Sheet :

mclk_in The MCLK input function, when it is connected to a pin by selecting it in the IOCON block

Does this mean, that it could be any IO Pin ?

But i need 2 Pins, Right?

One mclk_in  pin and one CLK_IN  pin ...

Andreas

[marek_neuzil]

Hi Andreas,

Yes, you need two input pins if you want to use the mclk_in as a reference clock source for the FLEXCOMM0 peripheral.

When you enable the mclk_in clock source the following warning is reported and you can use the context menu of the warning to route a pin for the mclk_in. The initialization code is provided (generated) in the Pins tool. You can select one of two routable pins for the mclk_in.

See the following screenshot:

Best Regards,

Marek Neuzil