K32L2B21: ADC0 reading simultaneously 3 channels

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K32L2B21: ADC0 reading simultaneously 3 channels

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nre
Contributor II

nre_0-1619191310581.png

Hello, I'm using microcontroller K32L2B21VFT0A (without MCUxpresso IDE), and I have to configure 3x ADC0 channels.
I also need to use these 3 channels asynchronously, trigerred by SW.
My questions are:

1) Is that possible to read simultaneously these 3 ADC0 channels by using DMA?
I saw that MCUXpresso config tools v9.0 generates erroneously the following code,
by missing the third channel. I configured 3 channels, but instead 2 channels are read in the auto generated code:

/* ADC0_IRQn interrupt handler */
void ADC0_IRQHANDLER(void) {
/* Array of result values*/
uint32_t result_values[2] = {0};
/* Get flags for each group */
for ( int i=0; i<2; i++){ //<--------!!!!!!!!!!!!!!!! WRONG ARRAY SIZE = 2 !!!!!!!!! It must be 3
uint32_t status = ADC16_GetChannelStatusFlags(ADC0_PERIPHERAL, i);
if ( status == kADC16_ChannelConversionDoneFlag){
result_values[i] = ADC16_GetChannelConversionValue(ADC0_PERIPHERAL, i);
}
}

/* Place your code here */

/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F
Store immediate overlapping exception return operation might vector to incorrect interrupt. */
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
}

I would like to ask if it's some HW limitation that i have to consider when using this specific microcontroller,
or it's just a wrong parameterization that I can set manually from 2 to 3.
In K32L2B21A.h there is a define "#define ADC_SC1_COUNT (2U)" that fixes this restriction to 2 channels. Is it a wrong value, or the channels are indeed limited to 2?

2) by using the auto generated code for reading out the 3x ADC0 channels, i am able to obtain values only for the first channel.
The values read from the other channels remain 0.
Is there some example code for DMA reading simultaneously all these 3 ADC0 channels?
Is the auto generated poposed code correct? Is it OK to read in a loop all these 3 channels of ADC0?
Or i have to read them sequentially, by reading only one ADC0 channel per interrupt?

3) In the documentation is written: "Channel group 1 and greater indicates multiple channel group registers for use only in hardware triger mode" (https://mcuxpresso.nxp.com/api_doc/dev/210/group__adc16.html#ga7b953a868efa27473910b72d7f80287c)
Does it mean that I can't use SW trigerring mode for reading all these 3 channels of ADC0 in one common interrupt for ADC conversion completion like this?
ADC16_SetChannelConfig(ADC0_PERIPHERAL, ADC0_CH0_CONTROL_GROUP, &ADC0_channelsConfig[0]);
ADC16_SetChannelConfig(ADC0_PERIPHERAL, ADC0_CH1_CONTROL_GROUP, &ADC0_channelsConfig[1]);
ADC16_SetChannelConfig(ADC0_PERIPHERAL, ADC0_CH2_CONTROL_GROUP, &ADC0_channelsConfig[2]);
where the three control groups are the same value, equal to 0.
If that's not possible, would you please suggest me some example or code to resolve this issue?
If I replace SW trigerring of ADC0 channels by HW one on a fixed period, would it fix my problem?

 

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jingpan
NXP TechSupport
NXP TechSupport

Hi nre,

I think the auto generated code is fine. ADC_SC1_COUNT means there are two SC1x register, SC1A and SC1B. Channel group means you can assign each channel to SC1A or SC1B in software. Here are some examples.

 

https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL17Z32VLH4-multiple-19ch-ADC-with-DMA/m-p/10...

https://community.nxp.com/t5/Kinetis-Microcontrollers/Code-Example-for-ADC16-IRQ-Handler/m-p/760517

 

Regards,

Jing

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180 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi nre,

I think the auto generated code is fine. ADC_SC1_COUNT means there are two SC1x register, SC1A and SC1B. Channel group means you can assign each channel to SC1A or SC1B in software. Here are some examples.

 

https://community.nxp.com/t5/Kinetis-Microcontrollers/MKL17Z32VLH4-multiple-19ch-ADC-with-DMA/m-p/10...

https://community.nxp.com/t5/Kinetis-Microcontrollers/Code-Example-for-ADC16-IRQ-Handler/m-p/760517

 

Regards,

Jing

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