How to handle SSELx pin in SPI procedure

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How to handle SSELx pin in SPI procedure

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_Ferrari_
Contributor IV

Dear all,

I'm using LPC5555S28-EVK and I'm configuring SPI device on FLEXCOMM4 using MCUXpresso IDE v11.5.1 [Build 7266] [2022-04-13].

I'm using SPI in MASTER and POLLING mode and I need to use two chip selects (SSEL0 and SSL1).But id I use the peripherals configurator tool, I can handle only once SSEL bit.

Browsing the software (function SPI_MasterInit in peripherals.c and function SPI_WriteData in fsl_spi.c), I also noticed that the SSEL bit is derived by g_configs[instance].sselNum that is initalizated in the SPI_MasterInit routine.

It means that if I use NXP SPI driver it is impossible to chenge the SSEL bit without reinit the SPI peripheral.

Did you have similar problem ? How did you fix it ?

Thank you very much for your help and cooperation

best regards

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1 Solution
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Alice_Yang
NXP TechSupport
NXP TechSupport

Hello,

 

There is no SDK for multiple SSEL so far.

I suggest you can use below code:

1. You need initialize the SPI SSEL pins in pin_mux.c

2.then use below code

static uint16_t LCD_WORD_WRITE(uint16_t data, uint8_t ssel)
{
uint32_t temp;
/* clear tx/rx errors and empty FIFOs */
// LCD_SPI->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
// LCD_SPI->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
LCD_SPI->FIFOWR = data | 0x0F300000 | (1<<(16+ssel) );
/* wait if TX FIFO of previous transfer is not empty */
while ((LCD_SPI->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) == 0) {
}
temp = (LCD_SPI->FIFORD | (1<<(16+ssel))&0x0000FFFF;
return temp;
}

 

BR

Alice

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4 Replies
1,420 Views
_Ferrari_
Contributor IV

Ok. thanj you !

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1,476 Views
_Ferrari_
Contributor IV

Dear Alice,

Thank you for your reply.

Just a question: I read on the UM11126.pdf pag.699 (rev 1.8) that the bit SSLx should be 0 to assert it. In the code that you sent me is the opposite (1 means assert bit)

Could you check, please ,from your side ?

regards

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1,463 Views
Alice_Yang
NXP TechSupport
NXP TechSupport

Hello,

Yes, by default, the  active state is low (0), while it can be configure in CFG, this just a piece of code from other application, you can refer to your requirements to config.

 

BR

Alice

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1,486 Views
Alice_Yang
NXP TechSupport
NXP TechSupport

Hello,

 

There is no SDK for multiple SSEL so far.

I suggest you can use below code:

1. You need initialize the SPI SSEL pins in pin_mux.c

2.then use below code

static uint16_t LCD_WORD_WRITE(uint16_t data, uint8_t ssel)
{
uint32_t temp;
/* clear tx/rx errors and empty FIFOs */
// LCD_SPI->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
// LCD_SPI->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
LCD_SPI->FIFOWR = data | 0x0F300000 | (1<<(16+ssel) );
/* wait if TX FIFO of previous transfer is not empty */
while ((LCD_SPI->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) == 0) {
}
temp = (LCD_SPI->FIFORD | (1<<(16+ssel))&0x0000FFFF;
return temp;
}

 

BR

Alice

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