Clock.c is crashing, Config tool is not set correctly

[Cdn_aye]

I have used the clock configuration tool to generate clock.c,h without any errors listed, MK20Dx256ZVll10. I have an external 8Mhz, 12pf xtal for the external req input and need USB and 96 Mhz for the processor. I have the generated files built into the project. However the code gives an assert in the  CLOCK_SetExternalRefClkConfig(oscsel); 

I am trying to run FreeRTOS on this board; it works fine with mqx, but I am unable to set the clocks with the tool. Is there a configured clock.c for this part someone could share or the .mex file. I can't seem to find a working example anywhere. A k40, k60 would also work if available. Thanks for any help

Robert

[Cdn_aye]

The code for the clock system is wrong. It will not work. You must correct the fsl_clock.c file, then call the state machine to set the clock up. This is not in the doc set that I can find, I found this by debugging the code. I will paste corrected code below. Note there are two defines you must define, one is for the Z series to bypass the checks (#ifdef MCG_C7_Z)the other is to bypass the error in the code and leave the original code intact, do a search for mcg_c7 and bypass in all the places(this is one example below). The second file is how to call the clock system correctly.

The code base for the sdk probably was never tested as a system, it will not run even the hello world program the way it is now. The clock cct is a cut and paste from working PE code, however the configurator does not allow for the fact that the clock is a state machine, they just pick a final state and call that. It will never run like that.

This mode is for the PEE mode, I haven't corrected any of the others.

Regards

Robert Lewis

////////////////////////////// clock_config.c ////////////////////////////////////////  FOR THE MCG_7 BYPASS DEFINE

/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const mcg_config_t mcgConfig_BOARD_BootClockRUN =
{
.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
.irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
.fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
.drs = kMCG_DrsLow, /* Low frequency range */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
.pll0Config =
{
.enableMode = kMCG_PllEnableIndependent,/* MCGPLLCLK enabled independent of MCG clock mode, MCGPLLCLK disabled in STOP mode */
.prdiv = 0x1U, /* PLL Reference divider: divided by 2 */
.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
},
};
const sim_clock_config_t simConfig_BOARD_BootClockRUN =
{
.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
.clkdiv1 = 0x1130000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /4 */
};
const osc_config_t oscConfig_BOARD_BootClockRUN =
{
.freq = 8000000U, /* Oscillator frequency: 8000000Hz */
.capLoad = (kOSC_Cap2P | kOSC_Cap16P), /* Oscillator capacity load: 18pF */
.workMode = kOSC_ModeExt, /* Use external clock */
.oscerConfig =
{
.enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,/* Enable external reference clock, enable external reference clock in STOP mode */
}
};

/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{

/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
OSC_SetExtRefClkConfig(OSC0, &oscConfig_BOARD_BootClockRUN);

CLOCK_SetMcgConfig(&mcgConfig_BOARD_BootClockRUN);

/* Configure RTC clock including enabling RTC oscillator. */
CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_12PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
/* Enable USB FS clock. */
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, SIM_USB_CLK_96000000HZ);
/* Set CLKOUT source. */
CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK);
}

//////////////////////////////////// fsl_clock.c /////////////////////////////////////////////// FBE mode is wrong //////////////////////////////

status_t CLOCK_SetFbeMode (uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
bool change_drs = false;

// SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; // **rwl, Select PLL
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
#ifdef SDK_MCG_BYPASS

SIM->CLKDIV1 = (uint32_t)0x01130000UL; /* Update system prescalers */
/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
SIM->CLKDIV2 = (uint32_t)((SIM->CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM->SOPT2 |= (uint32_t)0x00010000UL; /* Select PLL as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=1 */

SIM->SOPT1 |= (uint32_t)0x00080000UL; /* RTC oscillator drives 32 kHz clock for various peripherals */
MCG->C2 = (uint8_t)0x2DU;

MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
(MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */

mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
MCG->C4 = mcg_c4;

/* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=3 */ // will be set again later by CLOCK_EnablePLL0
MCG->C5 = (uint8_t)0x03U;
/* MCG_C6: LOLIE=0,PLLS=0,CME=0,VDIV=0x18 */
MCG->C6 = (uint8_t)0x18U;
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
}
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}

return kStatus_Success;
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

#else
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
mcg_mode_t mode = CLOCK_GetMode();
if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
(kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
{
return kStatus_MCG_ModeUnreachable;
}
#endif

/* Change to FLL mode. */
MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}

/* Set LP bit to enable the FLL */
MCG->C2 &= ~MCG_C2_LP_MASK;

mcg_c4 = MCG->C4;

/*
Errata: ERR007993
Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
reference clock source changes, then reset to previous value after
reference clock changes.
*/
if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
{
change_drs = true;
/* Change the LSB of DRST_DRS. */
MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
}

/* Set CLKS and IREFS. */
MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
(MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */

/* If use external crystal as clock source, wait for it stable. */
#ifndef MCG_C7_Z
if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
{
if (MCG->C2 & MCG_C2_EREFS_MASK)
{
while (!(MCG->S & MCG_S_OSCINIT0_MASK))
{
}
}
}
#elseif
while (!(MCG->S & MCG_S_OSCINIT0_MASK))
{
}
#endif

/* Errata: ERR007993 */
if (change_drs)
{
MCG->C4 = mcg_c4;
}

/* Set DRST_DRS and DMX32. */
mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));

/* Wait for clock status bits to show clock source is ext ref clk */
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U){}
while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
{
}

/* Wait for fll stable time. */
if (fllStableDelay)
{
fllStableDelay();
}
return kStatus_Success;
#endif
}

[marek_neuzil]

Hello,

I am sorry, but the MK20DX256ZVLL10 is not supported. The MK20DX256VLL10 is supported only, see the mcuxpresso.nxp.com website.

The problem is caused by using of the MK20DX256ZVLL10. This device does not contain the MCG_C7 register, see also the issue https://community.nxp.com/message/875013?commentID=875013#comment-875013 

I have also checked the issue of the FRDM-KL82Z7 board but it seems to be an issue of the application. It can be caused by missing initialization of the external oscillator before selection by the OSCSEL bitfield in the MCG_C7 register. The external oscillator is initialized by using following code (see also the BOARD_BootClockRUN() function:

    /* Initializes OSC0 according to board configuration. */
    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);

Best Regards,

Marek Neuzil

[kamiccolo]

Well, in case of FRDM-KL82Z7 generated example does contain the relevant external oscillator initialization:
/* Initializes OSC0 according to board configuration. */
CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);

I'm presuming that those are different for FS and HS modes. Neither of those are working though.

[Cdn_aye]

It is simple to make this work.

The default is the external oscil. Therefore bypass that check in the code.

The 7 and 8 registers were added after. The Z was a preproduction part.

make sure you return the correct status from the call.

Robert

[kamiccolo]

Got usb/virtual_com examples crashing on FRDM-KL82Z7 board on the same place. Backtrace:
#0 HardFault_Handler () at startup_MKL82Z7.S:235
#1 <signal handler called>
#2 0x00001ac4 in CLOCK_SetExternalRefClkConfig (oscsel=kMCG_OscselIrc)
at drivers/fsl_clock.c:692
#3 0x000023a6 in CLOCK_BootToBlpeMode (oscsel=<optimized out>)
at drivers/fsl_clock.c:1655
#4 0x00001128 in App_BootClockRUN () at virtual_com.c:156
#5 0x00006862 in main () at virtual_com.c:897

Using recently generated MCUXpresso Config Tools SDK for GCC-ARM.