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DDR tool for i.MX

NXP Employee
NXP Employee
0 0 664

This document introduces the double data rate (DDR) RAM configuration and validation tool, which is an embedded component of Config tools for i.MX.

The DDR tool has two components: DDR configuration tool and DDR validation tool. The DDR configuration tool allows you to create a configuration for the DDR component and the DDR validation tool allows you to validate the DDR configuration using various validation scenarios.


- Supports only MIMX8MM family

- Supports only LPDDR4

- Supports only one frequency setpoint

- Validation is not working on MacOS


- Configure the i.MX target board to boot in Serial Download Mode

- Connect UART cable from PC to board's debug UART port

- Connect USB cable from PC to board's USB OTG port 

- Generate the DDR configuration from Register Programming Aid tool (RPA)

DDR configuration


DDR configuration tool provides a user-friendly graphical interface to configure the DDR controller and the DDR PHY. It can be used for tweaking some of the configuration parameters when you want to use different DDR devices from different vendors or when you want to optimize the DDR configuration.  


To use the DDR configuration tool, you first need to create a new project for processor with DDR tool support.


Before starting with the DDR tool, make sure you have RPA tool for your processor and generate the output.

To create a project for DDR tool, follow these steps:

1. Once you start the Config tools for i.MX, you can create a new configuration from the welcoming window

pastedImage_6.png2. In the next step select the processor with DDR tool support


3. From the Config Tools Overview select the DDR

4. In DDR configuration view expand the DDRC component to view the configuration

5. Importing output from RPA tool is mandatory in this release of DDR tool. To do this, click on Import DDR Configuration button, browse for the .ds file and click OK


6. In Input data section imported DDR PHY parameters are displayed

7. In Registers View imported DDR controller registers are displayed


8. Once the output of RPA tool has been imported, you will see the PHY configuration in DDRC component under Phy Configuration. If configuration needs to be changed, you can do it from the UI


DDR validation

The DDR validation tool can be used to validate a DDR configuration using predefined scenarios. To start DDR validation tool, open Validation View (go to Views and click on Validation if the view is not open already).

1. There are several predefined scenarios used in validation process

Firmware Init will perform PHY initialization based on the parameters from the Phy Configuration.

Operational is a suite of tests for quick verification of DDR configuration using several tests as Write-Read-Compare, Walking Ones, Walking Zeros.

Stress Tests is a suite of tests meant to verify the performance and stability of the memory in a non-OS environment (beta version in this release).


2. For each test, except the Firmware Init, you can choose test parameters from Choose Tests tab


3. To start validation, you must select the correct COM port. Searching for available COM ports is available by click on Scan for available COM ports button


4. Select the Scenario and tests you want to run and click on Start Validation for running the tests on target board


5. Tests results are available in Results tab


6. To switch between simple and detailed log select the Real time option


7. To run vTSA tests go to Diags tab. Tx Eye (Diag Write Margin) and Rx Eye (Diag Read Margin) tests are available. You can select on which lanes to execute the test from Choose Tests parameters

   The TxEye test collects the transmit eye associated with a specifc byte and bit. The eye is measured by running traffic
   while varying the DRAM VREF and Phy’s TxDq delay settings. The test records how many errors occur at each delay and
   voltage setting and returns a matrix of encoded error counts.

   The RxEye test collects the receive eye associated with a specifc byte and bit. The eye is measured by running traffic
   while varying the Phy’s VREF and RxClkDly delay settings. The test records how many errors occur at each delay and
   voltage setting and returns a matrix of encoded error counts.

8. After the vTSA tests are done the Data Eyes will be displayed in Results


9. Test results can be saved as JPG by using Generate DDRV Report


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