MK22FN512 NXP_Kinetis_Bootloader_2_0_0 jump to APP sometimes successful sometimes failure.

[andypeng]

I use the device MK22FN512,want  using boot NXP_Kinetis_Bootloader_2_0_0,  jump to APP, but APP sometimes successful, sometimes failure.
NXP_Kinetis_Bootloader_2_0_0 compiler environment: Kinetis Design Studio Version: 3.2.0 
NXP_Kinetis_Bootloader_2_0_0 program start address: 0x0000,

The following is the address configuration：

MEMORY
{
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x0007FBF0
m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00020000
}

NXP_Kinetis_Bootloader_2_0_0 clock I have not modified.

APP compiler environment: Kinetis Design Studio Version: 3.2.0 

the following is the address configuration for APP：

/* Entry Point */
ENTRY(__thumb_startup)

/* Highest address of the user mode stack */
_estack = 0x20010000; /* end of m_data */
__SP_INIT = _estack;
__stack = _estack;

/* Generate a link error if heap and stack don't fit into RAM */
__heap_size = 0x00; /* required amount of heap */
__stack_size = 0x0400; /* required amount of stack */

MEMORY {
m_interrupts (RX) : ORIGIN = 0x0000A000, LENGTH = 0x00000198
m_text (RX) : ORIGIN = 0x0000A410, LENGTH = 0x00075BF0
m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00020000
m_cfmprotrom (RX) : ORIGIN = 0x0000A400, LENGTH = 0x00000010
}

APP uses the clock mode: PEE, the external crystal is 10MHz
From the NXP_Kinetis_Bootloader_2_0_0 start and then jump to the APP failed, through the emulator to observe, the error at the following address (CPU_Init.c):

When the APP program address is 0x0000, the following configuration does not have the above problem.

/* Entry Point */
ENTRY(__thumb_startup)

/* Highest address of the user mode stack */
_estack = 0x20010000; /* end of m_data */
__SP_INIT = _estack;
__stack = _estack;

/* Generate a link error if heap and stack don't fit into RAM */
__heap_size = 0x00; /* required amount of heap */
__stack_size = 0x0400; /* required amount of stack */

MEMORY {
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000198
m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x00075BF0
m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00020000
m_cfmprotrom (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
}

The following is a APP clock configuration：

APP project on attachment .

How is the cause of this problem? 

Thanks & regards

Andy ,China

Original Attachment has been moved to: LED_DEMO.7z.zip

[ramboyang]

Hi Andy,

Please try to replace the clock_switch() function in clock_config_K22F512.c with below one, hope it could be helpful:

void clock_mode_switch(const target_clock_mode_t currentMode, const target_clock_mode_t expectedMode)
{
// Note: here only implements clock switch between FEI and FEE,
// The other modes are not supported.
assert(currentMode == kClockMode_FEE || currentMode == kClockMode_FEI);
assert(expectedMode == kClockMode_FEE || expectedMode == kClockMode_FEI);

if (currentMode == expectedMode)
{
return;
}

if (expectedMode == kClockMode_FEE)
{
uint8_t tmp;
/* Switch to FEE mode */
tmp = MCG->C2;
tmp &= (uint8_t)~MCG_C2_RANGE_MASK;
tmp |= MCG_C2_RANGE(2);
MCG->C2 = tmp; /* MCG_C2: RANGE = 2 */

tmp = MCG->C1;
tmp &= (uint8_t) ~(MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK);
tmp |= MCG_C1_FRDIV(6);
MCG->C1 = tmp; // FRDIV=6, RANGE=2, divide IRC48M with 1280, switch to external reference clock.

tmp = MCG->C4;
tmp &= (uint8_t)~MCG_C4_DRST_DRS_MASK;
tmp |= MCG_C4_DRST_DRS(1);
MCG->C4 = tmp; // Multiply with 1280, MCGOUTCLK is 48Mhz

tmp = MCG->C7;
tmp &= (uint8_t)~MCG_C7_OSCSEL_MASK;
tmp |= MCG_C7_OSCSEL(2);
MCG->C7 = tmp; // Select IRC48M as Oscillator.

while (MCG->S & MCG_S_IREFST_MASK)
; // Wait until external reference clock is ready.
}
else if (expectedMode == kClockMode_FEI)
{
MCG->C1 |= MCG_C1_IREFS_MASK; // Switch to internal reference clock.
while (!(MCG->S & MCG_S_IREFST_MASK))
;

// Wait until internal reference clock is ready.

// Wait 2 cycles of the slow IRC + 2 cycles of OSCERCLK after MCG[IREFS]
// has been set to 1.
for (volatile uint32_t delay_cnt=0; delay_cnt < 16 * 1000; delay_cnt++)
{
__NOP();
}

// Restore registers to default value out of reset.
MCG->C1 = 0x04U;
MCG->C2 = 0x80U;

MCG->C4 &= (uint8_t)MCG_C4_DRST_DRS_MASK;
MCG->C7 = 0;
}
}

Best Regards,

Fan