the problem of ls1012A borad

[13540372905]

Hello, my question is as follows:

1. At present, we have encountered a problem when debugging the board made by ls1012a chip. Now it is suspected that the frequency doubling of Platform PLL in the system has not been successful, is there have any way to measure the output of Platform PLL?

2. We found that the chip has a CLK_OUT pin, which only defines SYSCLK from the register definition in the manual. But we also see such a description of CLK_OUT "The CLK_OUT signal can be configured to offer one of a variety of internal clock signals to external hardware for debug or diagnostic purposes". Can this pin be configured to output platform PLL clock? If yes, how do I configure it?

3. The block diagram of clock principle of ls1012a chip is as follows. See the figure below for SYSCLK and platform PLL above:

[Bulat]

1. Direct measurement is not possible. Indirectly you can measure DDR output frequency if MMDC is up.

2. CLK_OUT ouput can be set to SYSCLK clock (125MHz) and its derivatives (/2, /4, /8), but not to platform PLL one. See description of the CLKPCSR register for details.

Regards,

Bulat

[13540372905]

Thank you for your reply.

At present, we found that platform PLL frequency doubling failed; I want to know the Platform PLL frequency doubling is affected by that hardware?

[Bulat]

I am not quite sure what means "we found that platform PLL frequency doubling failed".  How did you find that?