reconfigure XIP mode to access bootflash for ls1043a

[lgx]

my project use the ls1043a cpu, there are 2 qspi flashes, separated attached to cs0 and cs1.

cs0 flash is bootflash, run on XIP mode.  cs1 flash is data flash.

During bootup,  it will copy load_firmware.bin to run in OCRAM, responsible for loading firmware from data flash (cs1) and then return to bootflash.

After accessing data flash using AHB mode, how could i reconfigure QSPI controller to access bootflash in XIP mode ?

[yipingwang]

Investigating.

[yipingwang]

QSPI flash is XIP mode so based on the address scheme you define for your system, when you access back the bootflash address range, you will be in XIP mode.
Is there something I am missing? Please detail if yes.

[lgx]

Hi Yiping,

I am not sure about that. From my perspective, QSPI controller need to be setting to a special state to realize XIP access.

After i access the CS1 data sNOR, i need to configure the QSPI controller to AHB/IP mode to READ/ERASE/Program.   The qspi controller is not in the initial state (maybe bootROM configure for bootflash)

[yipingwang]

Please provide more details on what issue is being faced.

Our RDB also has two flash and can be used for experimenting.

The QSPI flash is XIP which why it can be used as boot flash.

[lgx]

I have the similar requirements of "Multiple flash implementing RWW". cs0 is the boot sNOR, works on XIP mode, cs1 is the data sNOR.

https://www.nxp.com.cn/docs/en/application-note/AN12564.pdf

Do we have the demo logic to realize RWW on ls1043a ?

[yipingwang]

Would you please create a new thread to address you new requirement?

[lgx]

OK, thanks.

Create a new post

To implement Read-While-Write (RWW) functionality on the LS1043A SoC ? - NXP Community

[yipingwang]

Thanks a lot.