question related IFC Pins shifting T1042

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question related IFC Pins shifting T1042

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faizmajeed
Contributor III

Hi!

I have question related IFC Pins shifting. According to reference manual of T1042 Section : 24.4.1.2.1

"In this mode of muxing, the IFC supplies the most significant bit (msb) of the address bits
on the AD bus."

and they provided a picture i attached. now in reference schematics, there is some difference in pins assignment that instead of making AD0 as MSB, they have connected IFCA5 on MSB address bit of flash.

What are your recommendation that how we should connect it.

Thanks 

Manual_Snap.PNG

Schematics Snap.PNG#

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r8070z
NXP TechSupport
NXP TechSupport

The Figure 24-9 is not suitable for the T1042/T1040. It is for processor which provides the least significant address bit on pin named A26 in the mode 0. The T1042 does that on pin named IFC_A31 in this mode. The second picture looks like T1040RDB schematics where IFC_A[31:16] come from the T1042 IFC_A[31:16] and IFC_A[15:8], IFC_VA[7:5] are latched  from the T1042 IFC_AD[15:05]. It is correct for ADM mode 0

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