pcie COMPLIANCE test

[muaxi8]

Now our LX2180 board needs to perform pcie signal integrity test, but the pcie state machine cannot

enter POLL_COMPLIANCE state, it alaways in the detect_quiet state, and the COMPLIANCE state

kernel configuration is only imX.6/7/8

Is there a register that can configure the state machine to COMPLIANCE? Or otherwise configure the

COMPLIANCE status?

[ufedor]

For PCIe electrical compliance testing, the PCI-SIG offered two kinds of boards to facilitate the test for different device type/mode - RC in PC MB formfactor or EP in Plug-in Card formfactor:
· CBB w/Slot is for EP testing
o The CBB is in MB formfactor with slots so that the DUT EP can be plugged into the CBB slot for testing
· CLB w/Gold-Finger is for RC testing
o The CLB is in Plug-in Card formfactor so that it can be plugged into the DUT RC’s slot for testing

How exactly PCIe is connected in your case?

Please provide connection block diagram and corresponding U-Boot booting log as text file.

[muaxi8 · Accepted solution]

My question now is the same as this post

https://community.nxp.com/t5/Layerscape/LS1046A-PCIe-compliance-mode-set-speed-to-5Gbit-s/m-p/809940

2.5Gbit/s signal we can see that it is the first state of the pcie state machine. Now we want to configure

the status of LX2080 for Compliance to test the 5Gbit/s signal.

We are configured this way，But the 5Gbit/s signal is not visible.

a. Set the Target link speed bit field (T_LS) to the desired speed (0x2).

b. Set the Enter Compliance (EC) bit

[ufedor]

Please provide additional information:

1) the processor connection schematics as searchable PDF to check PCIe links connections

2) U-Boot booting log as text file.

3) which exactly PCIe controller is tested?

4) You wrote: "We are configured this way" - please provide corresponding log as text file.

[muaxi8]

1) The Uboot is attached

2) All six pcie controllers need to be tested. The current test is PCI 6.

3)

root@localhost:~# ./devmem

Usage: ./devmem { address } [ type [ data ] ]
address : memory address to act upon
type : access operation type : [b]yte, [h]alfword, [w]ord
data : data to be written

root@localhost:~# ./devmem 0x39000a0 h
/dev/mem opened.
Memory mapped at address 0xffffa6910000.
Value at address 0x39000A0 (0xffffa69100a0): 0x3
root@localhost:~#
root@localhost:~#
root@localhost:~# ./devmem 0x39000a0 h 0x13
/dev/mem opened.
Memory mapped at address 0xffffb22a2000.
Value at address 0x39000A0 (0xffffb22a20a0): 0x3
Written 0x13; readback 0x13
root@localhost:~# ./devmem 0x39000a0 h
/dev/mem opened.
Memory mapped at address 0xffff89496000.
Value at address 0x39000A0 (0xffff894960a0): 0x13
root@localhost:~#
root@localhost:~#
root@localhost:~# ./devmem 0x39C07FC h
/dev/mem opened.
Memory mapped at address 0xffff8cbb1000.
Value at address 0x39C07FC (0xffff8cbb17fc): 0x3

Compliance has been configured

[ufedor]

1) the processor connection schematics as searchable PDF to check PCIe links connections

2) In the provided "uboot-log.txt"

PCIe6: pcie@3900000 Root Complex: no link

Which CLB is used for the PCIe6?

[muaxi8]

The devices accompanying the signal integrity test do not need to be identified. I can confirm that our hardware design is ok because normal pcie storage devices and network cards can be identified。

I'm now plugging in a storage device，uboot log：
PCIe6: pcie@3900000 Root Complex: x4 gen3

=> pci 6
Scanning PCI devices on bus 6
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
06.00.00 0x1957 0x8d82 Bridge device 0x04

[ufedor]

From the log:

> Written 0x13; readback 0x13

For Gen2 it should be 0x12.

[muaxi8]

Yes, I know this, the output information of uboot was yesterday, we just changed the pcie slot, so there is

no corresponding