INFO: RCW BOOT SRC is QSPI
VERBOSE: Generic delay timer configured with mult=1 and div=25
INFO: RCW BOOT SRC is QSPI
VERBOSE: platform clock 700000000
VERBOSE: DDR PLL1 1600000000
VERBOSE: DDR PLL2 0
VERBOSE: Found static setting for rate 1600
INFO: Time before programming controller 4 ms
VERBOSE: Program controller registers
WARNING: Warning: Optimal CPO value not set.
VERBOSE: total size 2 GB
VERBOSE: Need to wait up to 640 ms
VERBOSE: Reading debug[9] as 0x19001900
VERBOSE: Reading debug[10] as 0x19001900
VERBOSE: Reading debug[11] as 0x1c001d00
VERBOSE: Reading debug[12] as 0x1d001d00
VERBOSE: cpo_min 0x19
VERBOSE: cpo_max 0x1d
VERBOSE: debug[28] 0x70006f
WARNING: Warning: A009942 requires setting cpo_sample to 0x42
NOTICE: [DBG] dram_size: 2147483648, 2 GB DDR4, 64-bit, CL=11, ECC off
INFO: Time used by DDR driver 276 ms
NOTICE: [DBG] dram_regions_info.num_dram_regions = 1
VERBOSE: Memory seen by this BL image: 0x10000000 - 0x10011000
VERBOSE: Code region: 0x10000000 - 0x10007000
VERBOSE: Read-only data region: 0x10007000 - 0x10009000
VERBOSE: DRAM Region 0: 0x80000000 - 0xfbdfffff
VERBOSE: Secure DRAM Region 0: 0xfbe00000 - 0xffffffff
NOTICE: BL2: v1.5(release):LSDK-20.04-dirty
NOTICE: BL2: Built : 19:59:12, Jan 21 2022
INFO: Configuring TrustZone Controller
VERBOSE: TrustZone : Configuring region 0 (TZC Interface Base=0x1500000 sec_attr=0x0, ns_devs=0x0)
INFO: Value of region base = ffe00000
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 1)...
VERBOSE: TrustZone : ... base = fbe00000, top = ffdfffff,
VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0x0)
INFO: Value of region base = 1ffe00000
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 2)...
VERBOSE: TrustZone : ... base = ffe00000, top = ffffffff,
VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff)
INFO: Value of region base = fbe00000
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 3)...
VERBOSE: TrustZone : ... base = 80000000, top = fbdfffff,
VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff)
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
VERBOSE: FIP header looks OK.
VERBOSE: Using FIP
INFO: Loading image id=3 at address 0xfbe00000
INFO: Image id=3 loaded: 0xfbe00000 - 0xfbe0c631
INFO: BL2: Loading image id 5
VERBOSE: FIP header looks OK.
VERBOSE: Using FIP
INFO: Loading image id=5 at address 0x82000000
INFO: Image id=5 loaded: 0x82000000 - 0x820b786c
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xfbe00000
INFO: SPSR = 0x3cd
VERBOSE: Argument #0 = 0x1000a3f8
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x1000a420
VERBOSE: Argument #4 = 0x227fffff
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Number of DRAM Regions = 1
VERBOSE: DRAM0 Size = 7be00000
INFO: SEC is disabled.
VERBOSE: Memory seen by this BL image: 0xfbe00000 - 0xfbe1b000
VERBOSE: Code region: 0xfbe00000 - 0xfbe0a000
VERBOSE: Read-only data region: 0xfbe0a000 - 0xfbe0c000
VERBOSE: DRAM Region 0: 0x80000000 - 0xfbdfffff
VERBOSE: Secure DRAM Region 0: 0xfbe00000 - 0xffffffff
NOTICE: BL31: v1.5(release):LSDK-20.04-dirty
NOTICE: BL31: Built : 19:59:16, Jan 21 2022
NOTICE: Welcome to LS1046 BL31 Phase
INFO: ARM GICv2 driver initialized
VERBOSE: Leave arm_bl31_platform_setup
INFO: BL31: Initializing runtime services
[DBG-mem] uboot start:
[0x0x82000000]: 0x0a
[0x0x82000001]: 0x00
[0x0x82000002]: 0x00
[0x0x82000003]: 0x14
[0x0x82000004]: 0x1f
[0x0x82000005]: 0x20
[0x0x82000006]: 0x03
[0x0x82000007]: 0xd5
[0x0x82000008]: 0x00
[0x0x82000009]: 0x00
[DBG-mem] uboot end:
[0x0x820b7862]: 0x6e
[0x0x820b7863]: 0x75
[0x0x820b7864]: 0x6d
[0x0x820b7865]: 0x2d
[0x0x820b7866]: 0x6c
[0x0x820b7867]: 0x61
[0x0x820b7868]: 0x6e
[0x0x820b7869]: 0x65
[0x0x820b786a]: 0x73
[0x0x820b786b]: 0x00
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x82000000
INFO: SPSR = 0x3c9
VERBOSE: Argument #0 = 0x0
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0
NOTICE: [DBG] el3_exit success
U-Boot 2019.10 (Jan 21 2022 - 17:24:29 -0800)
SoC: LS1046A Rev1.0 (0x87070110)
Clock Configuration:
CPU0(A72):1800 MHz CPU1(A72):1800 MHz CPU2(A72):1800 MHz
CPU3(A72):1800 MHz
Bus: 700 MHz DDR: 1600 MT/s FMAN: 800 MHz
Reset Configuration Word (RCW):
00000000: 0e100012 10000000 00000000 00000000
00000010: 11338888 f0000002 40000000 c1000000
00000020: 00000000 00000000 00000000 0003e879
00000030: 20104505 00061002 00000096 00000001
Model: LS1046A RDB Board
Board: LS1046ARDB, boot from Invalid setting of SW5
CPLD: V0.0
PCBA: V0.0
SERDES Reference Clocks:
SD1_CLK1 = 100.00MHZ, SD1_CLK2 = 100.00MHZ
DRAM: VERBOSE: Handling SMC SIP_SVC_MEM_BANK.
VERBOSE: Handling SMC SIP_SVC_MEM_BANK.
VERBOSE: Handling SMC SIP_SVC_MEM_BANK.
1.9 GiB (DDR4, 64-bit, CL=11, ECC off)
SEC0: RNG instantiated
Using SERDES1 Protocol: 4403 (0x1133)
Using SERDES2 Protocol: 34952 (0x8888)
NAND: 0 MiB
MMC: FSL_SDHC: 0
Loading Environment from SPI Flash... unrecognized JEDEC id bytes: c8, 60, 18
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
EEPROM: Read failed.
In: serial
Out: serial
Err: serial
Net: unrecognized JEDEC id bytes: c8, 60, 18
SF: probe for ucode failed
Fman1: Data at 00000000f7a38330 is not a firmware
PCIe0: pcie@3400000 Root Complex: x4 gen2
PCIe1: pcie@3500000 disabled
PCIe2: pcie@3600000 disabled
No ethernet found.
Hit any key to stop autoboot: 0