ls1021aqds uboot nand boot

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ls1021aqds uboot nand boot

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shunpinglin
Contributor III

ls1021aqds NAND boot, firstly copy 8KB from NAND flash to IFC SRAM, then CPU execute in this SRAM.

I compiled the uboot and the size of uboot is > 8KB

-rw-rw-r-- 1 splin splin 35436 10月 12 14:31 u-boot-spl.pbl

 

So I think uboot must copy this code to SDRAM and change to execute in the SDRAM,

but I can't find the code in ls1021aqds.c . why?

I confused that the board_init_f() in ls1021aqds.c directly call board_init_r(NULL, 0).

the ls1021aqds board don't have enough space in IFC SRAM.

does anyone know the reson?? ?  Thanks!

The following is board_init_f(),which is called by ENTRY(_main) of crt0.S

#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;

#ifdef CONFIG_NAND_BOOT
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;

/*
* There is LS1 SoC issue where NOR, FPGA are inaccessible during
* NAND boot because IFC signals > IFC_AD7 are not enabled.
* This workaround changes RCW source to make all signals enabled.
*/
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
DCFG_CCSR_PORSR1_RCW_SRC_I2C);
out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
pinctl);
#endif

/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);

#ifdef CONFIG_FSL_IFC
init_early_memctl_regs();
#endif

get_clocks();

#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif

preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif

major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);

dram_init();

/* Allow OCRAM access permission as R/W */
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif

board_init_r(NULL, 0);
}
#endif

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keestrommel
Contributor IV

The SPL U-Boot  (size 15KB) is loaded in the OCRAM (On Chip RAM, size 64KB) of the LS1021A, so there is sufficient space.

Take into account that the SPL U-Boot is loaded into OCRAM using the PBL (Pre-Boot Loader) of the LS1021A. PBL is a list of register addresses and values read by the LS1021A when the LS1021A comes up after an reset (before the U-Boot has started).

When the QoriQ Linux SDK is configured to build a NAND boot an image "u-boot-with-spl-pbl.bin" is generated that includes a PBL coded SPL U-Boot. This image must flashed into first blocks of the NAND device.

471 Views
shunpinglin
Contributor III

hello,

   Thank you for your help, now I still have a bit confused.

     In 4.4.1 Power-on reset sequence of ls1021a document,

     15. If the IFC's NAND Flash interface is:
            • configured as the pre-boot initialization source
            OR
            • the boot device target AND not fused as secure boot
            AND
             • the IFC's NAND Flash interface was NOT previously used as the RCW source,
               then the reset block informs the IFC to load a boot block from Flash into the
               internal buffer RAM of the IFC. Once complete, the IFC signals back to the reset
                block, and the reset block can proceed. Note that if the IFC reports an ECC error,
               the device reset sequence is halted indefinitely, waiting for a hard reset or PORESET_B.

the document tell that copy boot code to internal RAM of the IFC. when the PBL copy boot code to OCRAM? I don't find any description about that.

please help

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shunpinglin
Contributor III

I see the document(LS1021ARM.pdf) that copy code to IFC SRAM. 

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Pavel
NXP TechSupport
NXP TechSupport

Look at the following document:

https://www.denx.de/wiki/pub/U-Boot/MiniSummitELCE2013/tpl-presentation.pdf

 

Find information about SPL in u-boot Readme. This file is available in u-boot source folder.


Have a great day,
Pavel Chubakov

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