ls1021a: Enhanced Optimization Register

[renaud]

Eventually got to start debugging our LS1021A based porotype.

it fails very early on writing to ddr->eor (0x108_0c00).

/* disable the re-ordering in DDRC */

ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);

I do not find a description of this register in the LS1021A manual Rev 3.1. 

I can access register sets such as DCFG, IFC but not the DDR controller. Though, it is not disabled as per DCFG_CCSR_DEVDISR5. My ls1021a-iot has not this problem.

Has anybody seen this issue?

[renaud · Accepted solution]

We did find the issue. The DDR reference clock was set to DDRCLK instead of DIFF SYSCLK. After that we had access to the DDR registers