eDMA issues on LS1043

[jdubie]

Hi! 

I tried to follow the example here: 

https://community.nxp.com/t5/Layerscape/LS1021-EDMA-single-request-in-u-boot/m-p/938086

but I keep getting DAE and DOE registers even though I'm following the example as close as I can? Am I missing something? Thanks for the help!

=> mw.l 0x1510008 0000ff00 1 <- 0x00ff0000 OCRAM1
=> mw.l 0x151000C ff000000 1 <- 0x000000ff OCRAM2
=> mw.l 0x10000000 0x0000ADDE 100 <- 0xDEAD0000
=> mw.l 0x10010000 0xBBBBBBBB 100
=> mw.l 2c0000c ffffffff 1; <- Enable the error Interrupt
=> mw.l 2c00014 ffffffff 1; <- Enabling all the channels to accept hardware requests
=> mw.l 2c01000 00000010 1; <- 0x10000000 source address
=> mw.l 2c01004 02020400 1; <- 2 destsize 2 ssize 4 src_mnr_loop_offset
=> mw.l 2c0100C 00ffffff 1; <- -(data size)
=> mw.l 2c01010 00000110 1; <- destaddress 0x10010000 destination address 
=> mw.w 2c01014 0400 1; <- 4 dst_mnr_loop_offset
=> mw.w 2c01016 0100 1; <- BITER
=> mw.w 2c0101c 0800 1; <- disable_after_major_loop
=> mw.w 2c0101e 0100 1; <- CITER
=> mw.l 2c01018 00ffffff 1; <- -(data size)
=> mw.l 2c01008 00010000 1; <- data size
=> mw.b 2c10000 00; <- clear dma channel first
=> mw.b 2c10000 bf; <- DMAMUX = 1, Source ID=63, always enable
=> md.b 2c0002c 4; md.b 2c00004 4;
02c0002c: 00 00 00 01 ....
02c00004: 80 00 00 30 ...0
=> md.b 10000000 10;
10000000: de ad 00 00 de ad 00 00 de ad 00 00 de ad 00 00 ................
=> md.b 10010000 10;
10010000: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb ................
=>

No transfer occurred and get errors in channel 0. Any input would be greatly appreciated!

Jacob

[ufedor]

U-Boot displays data in big-endian, so it is needed to byte-swap only data written into modules having LE registers.

eDMA is a big-endian module, so the following is not correct:

=> mw.l 2c01000 00000010 1; <- 0x10000000 source address

Should be:

=> mw.l 2c01000 0x10000000

etc.

[jdubie]

ufedor,

Thanks for the quick reply! Right its a big endian module but the way u-boot does mw.l it is big endian. for example the default for 2c0_0000 is 0x00000400 and when I do the following it is writing in big endian. Are there certain regs that need to be little endian vs big endian? I'm assuming all the regs in this processor are big endian?

on reset:
=> md.b 2c00000 4
02c00000: 00 00 04 00 ....
=> mw.l 2c00000 00040000 1 
=> md.b 2c00000 4
02c00000: 00 00 04 00 ....
=>

Let me know if there is something I'm missing... thanks!

Jacob

[ufedor]

Please refer to the QorIQ LS1043A Reference Manual, Table 2-3. CCSR Block Base Address Map.

[johnschmoller]

Hello Fedor,

In the end, we're trying to move data from NOR Flash attached to the IFC to DRAM. I think this follows what you said earlier. But the DMA cycle does not begin.

mw 2c01000 0 10; #Clear reg block
mw.b 2c10000 bf; #Enable DMA MUX, always enabled
mw.w 2c0101e 0001; #Set BITER to 1
mw.w 2c01016 0001; #Set CITER to 1
mw 2c01008 01000000; #Set transfer size to 0x1000000
mw 2c01000 68500000; #Set source addr to NOR Flash
mw.w 2c01004 0004; #Set source offset to 4
mw.w 2c01006 0202; #Set source and destination width to 32-bit
mw 2c01010 81000000; #Set destination do DRAM
mw.w 2c01014 0004; #Set destination offset to 4
mw.w 2c0101c 0001 #Start;

But we get the following results, no data was moved. Do you see what we're doing wrong?
=> md 68500000
68500000: edfe0dd0 3c6adc01 38000000 5866dc01 ......j<...8..fX
68500010: 28000000 11000000 10000000 00000000 ...(............
68500020: 74000000 2066dc01 00000000 00000000 ...t..f ........
68500030: 00000000 00000000 01000000 00000000 ................

=> md 81000000
81000000: deadbeef deadbeef deadbeef deadbeef ................
81000010: deadbeef deadbeef deadbeef deadbeef ................
81000020: deadbeef deadbeef deadbeef deadbeef ................
81000030: deadbeef deadbeef deadbeef deadbeef ................

=> md 2c01000
02c01000: 68500000 02020004 01000000 00000000 ..Ph............
02c01010: 81000000 00010004 00000000 00010001 ................
02c01020: 00000000 00000000 00000000 00000000 ................
02c01030: 00000000 00000000 00000000 00000000 ................

[ufedor · Accepted solution]

Please refer to the attached memory-to-memory eDMA example attached.

[jdubie]

Fedor,

Thanks a lot for this example. It now works on our board! We see what you mean by the endianess now. 

Best Regards,

Jacob