confuse about QuadSPI ref clk

[changbaoma]

Hi， all

   I notice there is a figure about QuadSPI, and it specify ref use "cluster1 clk". see below.

   

But at ls1021a dts, qspi clocks ref to platform_clk's "platform-clk-div2", and  platform_clk ref to fixed-clock "sysclk" , as i know the sysclk is fixup to 100MHz at u-boot phare.

And there is another about QuadSPI, Is it says QuadSPI clk  can be ref to "platform clk" or "cluster1 clk"?  and how can we choice those ref clk?

and why ls1021a dts choice sysclk(100MHz) as qspi's the ref clk ? 

(actually i find the QSPI_CLK is depend  on CPU clock only, when i change the cpu freq by /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor at run time )

[r8070z]

According to the LS1021A manual in the RCW phase QSPI gets sysclk and in the PBI Phase/Boot Phase it gets the core clock1. See 29.1.5 LS1021A QuadSPI module special consideration (LS1021ARM rev.3). It seems manuals Figure 4-8. “Clock subsystem block diagram - IP modules” reflects that.

If we look at

 platform_clk: pll@c00 {

                                                            compatible = "fsl,core-pll-clock";

                                                            #clock-cells = <1>;

                                                            reg = <0xc00>;

                                                            clocks = <&sysclk>;

                                                            clock-output-names = "platform-clk", "platform-clk-div2";

we can find that "platform_clk" label actually points to the core pll clock. It also can confuse me. For device tree we should refer to corresponding binding documentation described which properties are accepted and its values. I have not checked  but can suppose  that "platform-clk", "platform-clk-div2"; corresponds to the Figure 4-7. “Clock subsystem block diagram - cluster group A” where C1_PLL_SEL selects direct and ½ options.