Why are +CPU_VDD and +SVDD separate on LS1046ARDB ?

[sabine_s]

On the LS1046ARDB board, VDD and SVDD are generated separately, derived from +CPU_SVDD and +SVDD on the schematic.

Is there a reason why SVDD was not supplied from the same power supply as VDD?

[alexander_yakov]

SVDD is power supply for SerDes block. According to LS1046A device datasheet, SerDes block power supply should be applied in second step of recommended power supply ordering. So, even if core power supply and SerDes power supply are the same in voltage, they can not be applied simultaneously, so they are separated.

Please see LS1046A Datasheet, Section 3.2 "Power Sequencing" for details.

Have a great day,
Alexander
TIC

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[sabine_s]

Looking in that section it lists: "2. VDD, SVDD, TA_BB_VDD, USB_SDVDD, USB_SVDD" but it also says that "Items on the same line have no ordering requirement with respect to one another".

Could there be another reason why the RDB uses two separate supplies? And could we get by with using just one?

[alexander_yakov]

The LS1046A processor has two different power supply inputs (group of inputs) for main core VDD and for Serdes block SVDD. Theoretically, if these two voltages have the same requirement for voltage value and may be applied simultaneously, than you can source these two inputs from the same power supply. Having these two inputs separated on the processor allows separating power supply traces and filtering circuits for relatively more noisy core VDD and for more sensitive to noise Serdes power SVDD. 

I do not see "Design Checklist" available for LS1046 processor, this processor is quite new.

Please refer to Design Checklist for LS1043A processor (application note AN5012) for Serdes power filtering recommendations:

SerDes power supply filtering

The ferrite beads should be placed in parallel to reduce voltage droop. For the linear or low-noise switching
regulator, 10 mVp-p, 50 kHz to 500 MHz is the noise goal. All traces should be kept short, wide, and direct.
Use small area fill, if possible. The goal is to lower the impedance of this net, thus lowering the noise.
S1VDD may be supplied by linear or low noise switching regulator or sourced by a filtered VDD.
Two example solutions for S1VDD filtering, where S1VDD is sourced from VDD, linear or low noise switching
regulator, are illustrated in Figure 3 and Figure 4. Users can choose either one as they see best fit their
needs, but the primary NFM type filter has two advantages: lower DC droop and easier layout than the
ferrite bead solution.