TFA on LS1012A noSEC

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TFA on LS1012A noSEC

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Contributor I

Hi,

We have a design with  LS1012ASN7HKA-800MHz (NoSEC)  that works very well with the PPA in earlier LSDK releases. When trying to get LSDK 1909 running on this board, the boot loader stalls at BL2 when trying to load BL31. We added some additional debug output and see that BL31 is never started. The build works very well on the LS1012ardb we based our design on. How do we get the TF-A to load u-boot?

Thanks,

Eivind

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199 Views
Contributor I

Hi Yiping,

We already did that - same mmdc struct in atf as we had in u-boot ( .mdctl = 0x04180000, PLAT_DEF_DRAM0_SIZE     0x20000000).

The RCW is the same as before, and very similar to the RDB RCW.

Could the problem be related to the fact thas this chip is not SEC enabled, and that initialisation of SEC features happens in BL31?

Regards,

Eivind

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NXP TechSupport
NXP TechSupport

Hello Eivind,

There should be no relation with the SEC module.

Would you please try whether BL31 can start up when copying BL31 to OCRAM rather than DDR DRAM?

For example, modify BL31 base address as the following in plat/nxp/soc-ls1012/ls1012ardb/platform_def.h.

#define BL2_BASE                NXP_OCRAM_ADDR
#define BL2_LIMIT               (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE/2)
#define BL2_TEXT_LIMIT          (BL2_LIMIT - NXP_ROM_RSVD - CSF_HDR_SZ)


#define BL31_BASE               NXP_OCRAM_ADDR + NXP_OCRAM_SIZE/2
#define BL31_SIZE               (0x200000)
#define BL31_LIMIT              (BL31_BASE + BL31_SIZE)

Thanks,

Yiping

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199 Views
Contributor I

Hi Yiping,

There's no space in OCRAM1+OCRAM2 (64K + 64K) for BL2 and BL31

By the way: Where is TEST_BL31 defined?

Best regards,

Eivind

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199 Views
Contributor II

I have a very similar problem with ls1043a and custom board.  

Boot log as follow:

INFO: RCW BOOT SRC is QSPI
INFO: RCW BOOT SRC is QSPI
INFO: Time before programming controller 0 ms

NOTICE: 2 GB DDR?, 32-bit, CL=11, ECC off
INFO: Time used by DDR driver 11 ms
NOTICE: BL2: v1.5(release):LSDK-19.09-dirty
NOTICE: BL2: Built : 17:17:21, Jan 14 2020
INFO: Configuring TZASC-380
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xfbe00000
INFO: Image id=3 loaded: 0xfbe00000 - 0xfbe0b631
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x82000000
INFO: Image id=5 loaded: 0x82000000 - 0x820b060b
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xfbe00000
INFO: SPSR = 0x3cd   --­>  HANG...

DDR looks ok with QCVS.  We'll run tests with larger test area just in case...

I will also try to test with TEST_BL31 and let you know.

Anyway, if you find the root cause, please keep us posted.

Regards.

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Contributor II

You might have solve your problem already.  If not, this is what worked for me. One of the early u-boot init function was not crashing and because they execute before the console port is initialized, I was getting no output.

I did set a breakpoint in function "static inline int initcall_run_list()" in file u-boot/include/initcall.h and was able to find the problem.

You can look at this other post for some "missing link" about how to debug u-boot in CW. 

JTAG load and execute u-boot on LS1043a and CodeWarrior with custom RCW/DRAM init 

Regards,

Frank

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NXP TechSupport
NXP TechSupport

Hello Eivind,

Please define TEST_BL31 as 1 in atf/plat/nxp/soc-ls1012/ls1012ardb/platform_def.h.

In addition, you could use CodeWarrior to verify whether DDR memory works normally.

You could connect CodeWarrior to the target board with CodeWarrior TAP or configuring the target board as CMSIS DAP mode.

Please create a bareboard project and check whether the sample program can run successfully in DDR memory.

Please refer to C:\Freescale\CW4NET_v2019.01\CW_ARMv8\ARMv8\Help\Getting_Started_for_CW_ARMv8.pdf.

Thanks,

Yiping

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NXP TechSupport
NXP TechSupport

Hello Eivind,

In the TFA boot flow, DDR initialization is not required in U-Boot. DDR initialization is a part of TFA.

DDR init code can be added to <atf_dir>/plat/nxp/soc-<soc-name>/<soc-name>ardb/ddr_init.c.

Please customize the following configuration for your custom board in packages/firmware/atf/plat/nxp/soc-ls1012/ls1012ardb/ddr_init.c.

        static const struct fsl_mmdc_info mparam = {
                .mdctl = 0x05180000,
                .mdpdc = 0x00030035,
                .mdotc = 0x12554000,
                .mdcfg0 = 0xbabf7954,
                .mdcfg1 = 0xdb328f64,
                .mdcfg2 = 0x01ff00db,
                .mdmisc = 0x00001680,
                .mdref = 0x0f3c8000,
                .mdrwd = 0x00002000,
                .mdor = 0x00bf1023,
                .mdasp = 0x0000003f,
                .mpodtctrl = 0x0000022a,
                .mpzqhwctrl = 0xa1390003,
        };

In atf/plat/nxp/soc-ls1012/ls1012ardb/platform_def.h

define DDRC_NUM_CS             1       /* use 1 chip-select */

#define PLAT_DEF_DRAM0_SIZE     0x40000000      /*  1G */

Please customize RCW file in packages/firmware/rcw/ls1012ardb/R_SPNH_3508/ for you custom board.

Then regenerate ATF images.

Thanks,

Yiping

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