Stuck In Reset On QSPI Boot After Reading 8 Bytes

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Stuck In Reset On QSPI Boot After Reading 8 Bytes

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tyler-thomas
Contributor II

We are working on a board using Rev 2.0 of the LS1021A but seem to be running into a problem with QSPI booting.

As per reference manual F, the LS1 will search for the RCW at byte offset 0 of NOR.

We have used a programmer to write, and successfully read back, the PBL (preamble, RCW, and PBI's) to byte offset 0 of NOR.

However, the LS1 continually reads 8 bytes (probed and confirmed that they are the first 8 bytes which we programmed) before resetting itself.

  1. Does the LS1 expect something other than the preamble to be at byte offset 0 of NOR?

  2. Is there a way to build a PBL for QSPI in Linux SDK for LS1021A v0.4? (setting UBOOT_CONFIG ??= "qspi" in ls1021atwr.conf does not do so)

Thank you in advance!

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kladu
Contributor II

Hi Tyler,

PBL obviously does not sample the preamble of RCW correctly.

Check the endianess of your data in QSPI. Endian boundary is 64 bits. Also, rev1 of silicon had issue with timing on QSPI while in PBL. I don't know is this issue still persists in rev2 silicon (it should not), but you can try adding 22p cap to QSPI_DIO_A0 to fix that.

Regards,

Borut

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sinanakman
Senior Contributor III

Hi Tyler

I assume this is your custom board. Can you

post your RCW_SRC bootstrap pin settings and

the RCW that you programmed into your SPI NOR ?

Regards

Sinan Akman

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tyler-thomas
Contributor II

Hello Sinan.

You are correct, this is a custom board.

CFG_RCW_SRC0 = 0

CFG_RCW_SRC1 = 0

CFG_RCW_SRC2 = 1

CFG_RCW_SRC3 = 0

CFG_RCW_SRC4 = 0

CFG_RCW_SRC5 = 0

CFG_RCW_SRC6 = 1

CFG_RCW_SRC7 = 0

CFG_RCW_SRC8 = 0

This follows the documentation's required format for QSPI of 0_0100_010X.

The first 72 Bytes in SPI NOR are:

AA55AA55 01EE0100
08080010 00000000 00000000 10000000
10000000 08007922 40025A00 81046000
00000000 00000000 00000000 2003E800
00004504 24BB3140 00000000 00000000

But after reading the first 8 bytes, the LS1 goes into reset.

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kladu
Contributor II

Hi Tyler,

PBL obviously does not sample the preamble of RCW correctly.

Check the endianess of your data in QSPI. Endian boundary is 64 bits. Also, rev1 of silicon had issue with timing on QSPI while in PBL. I don't know is this issue still persists in rev2 silicon (it should not), but you can try adding 22p cap to QSPI_DIO_A0 to fix that.

Regards,

Borut

1,239 Views
tyler-thomas
Contributor II

This turned out to be the issue.

Performing a 64-bit byte swap to the PBL such that "AA55AA55 01EE0100" became "0001EE01 55AA55AA" allowed the rest of the PBL to be read.

At this point, we have inserted our custom RCW into ls102xa_rcw_sd.cfg in Linux SDK for LS1021A v0.4, taken the PBL from the resulting u-boot-ls1021atwr-2014.07-r0.bin, performed a 64-bit byte swap, and programmed this to SPI NOR. As to be expected, booting fails when the Secondary Program Loader tries to read U-Boot from the SD card.

While possible and partially complete, this process seems a little roundabout. Is there a way to use the SDK to build a PBL for SPI NOR? (setting UBOOT_CONFIG ??= "qspi" in ls1021atwr.conf does not do so)

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sinanakman
Senior Contributor III

Hi Tyler

Good to hear you found the problem.

I am just curious, when you say

"We have used a programmer to write ..."

what programmer did you use. I'd expect

the programmer would have done a "swap"

based on the a choice of endianess. Was

there an option for this ?

Regards

Sinan Akman

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tyler-thomas
Contributor II

We are using an Asix Forte Programmer. No endianess swap is performed and there is no option for it. While needing to manually swap bytes isn't convenient, it's certainly not the most important of our concerns.

At the moment, the only PBL we can build using the SDK is one for booting from SD. Is anyone aware of a way to build a PBL for booting from SPI NOR?

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sinanakman
Senior Contributor III

Hi Tyler

Thanks for the follow up. At this point

the mainline u-boot (which I primarily

use) does not generate  RCWs for NOR

(as well as SPI NOR). In the  case of NOR

it expects that RCWs that are shipped with

the board or generated by SDK will be used.

I will send a patch in the coming days to mainline

u-boot to generate an rcw.bin file that is

known to work for NOR boot and I'll see

if I can extend this to SPI NOR with the

right endianess as well.

Regards

Sinan Akman

1,239 Views
prabinca4u
Contributor III

Hi Sinan

Im also working in ls1021a-IOT board(REV 1). I know that it wont support QSPI booting on REV1. So I'm ordered REV 2 board. In that I need to boot up from QSPI. So can you pls send me the patches to generate the RCW.bin for QSPI(Where the RCW.bin is not generating for QSPI after bitbaking, but it is generating for SD card).

Thanks In advance.......!

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sinanakman
Senior Contributor III

In addition, can you please verify that GROUP B PIN

CONFIGURATION (BITS 384-415) of RCW reflects the

SPI pin connections in your design ?

Regards

Sinan Akman

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tyler-thomas
Contributor II

Yes, the Group B Pin Configuration is set appropriately.

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sinanakman
Senior Contributor III

Tyler, when you mention "the LS1 continually reads 8 bytes",

do you mean the preamble and the sysaddr or does it actually

read the first 8 bytes of RCW (i.e. 08080010 00000000) ?

Regards

Sinan Akman

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tyler-thomas
Contributor II

Just the preamble and sysaddr.

After reading "AA55AA55 01EE0100", it resets and repeats reading the same 8 bytes.

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