Dear Team,
We are currently facing an issue with the SPI interface. The chip select (CS) line is expected to remain high by default; however, it is observed to be low, and there is some unexpected toggling during the boot process.
For your reference, we have attached the Device Tree Source (DTS) node,, and necessary changes are made in the RCW.
DTS File
&dspi2 {
status = "okay";
spidev@1 {
status = "okay";
compatible = "spidev"; # we have also tried setting the compatibility to rohm,dh2228fv
reg = <1>;
spi-max-frequency = <15000000>;
};
};
RCW Fields.
IIC5_PMUX=3
SDHC1_DIR_PMUX=3
SDHC1_DS_PMUX=2
Please Note: CLK, MOSI are generated correctly but CS isn't working the same.


SPI3_SOUT i.e. SPI 3 is used in the board.
The Yellow is Chip select, Green Data(MOSI), Pink Clock and Blue DIO (MISO)
This is a zoomed out image to show the time gap between Chip select Going low and the Incoming Data

Zoomed in version green as MOSI and yellow as Clock.
why is SPI driver is generating so much delay between CS-CLK.

Thanks,
Shivam