SD_CLK rise time is too slow

[carljones]

Hello NXP Community,

I would like to consult on a problem with my LS1043A custom board. The board boots from the SD Card. Most of the boards boot properly up to the Linux user space. However, I have two new boards that fail to boot at all. I noticed that they only fail to boot when EVDD is <3.4V and the SD_CLK signal looks like it was configured as open drain.

My problem is, some boards that initially worked and were deployed came back with this same problem. Below are the relevant schematic diagrams and configuration details.

*the SEL_EVDD is fed to a CPLD that outputs the SEL_EVDD_SW

*here’s the waveform of the failing board. Blue is SD_CLK, Green is SD_DATAn

What can cause the rising edge of the SD clock to be ~20ns instead of the 3ns required by the SD spec?

Thank you in advance.

Kind regards,
Carlos

[June_Lu]

Please check if the power change meet the SPEC.

Please confirm you give the SEL_EVDD a default voltage before the RCW has been load.

As no rising time error on LS1043ARDB, so please compare the EVDD control between them, especially the POR start.

Confirm the "a few times" are which steps of the 4.4.1 Power-on reset sequence, LS1043A Reference Manual.

[carljones]

Appreciate the assistance, June Lu. We'll verify and give feedback. Thanks

[June_Lu]

Please refer to LS1043ARDB CPLD source for the EVDD control.

Another possible way to debug the issue, maybe you could disconnect the resistor R72 to find out which part(TX or RX) cause the issue. which may help to figure out the issue quickly.

[IA]

How can the EVDD control affect the clock's rising edge? The EVDD voltage switches during the boot, which does not start. The problem is with the clock rising edge time being out of spec. The R72 was shorted, and it did not help. The clock rising edge time changes significantly (a few times) with small changes in 3.3V (100-200mV).