Rx echo with lpuart on LS1027A

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Rx echo with lpuart on LS1027A

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Bruno_Rodrigues485
Contributor I

Hello. I'm using processor LS1027A and serial driver fsl_lpuart from linux-5.4.47-rt28. The driver says it doesn't support setting the RS485 configuration receiving during transmiting (RX_DURING_TX). Is it possible to disable the RX_DURING_TX? Or is it not implemented due to some peripheral limitation? We need this "echo" configurable for our application.

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Bruno_Rodrigues485
Contributor I

Hello, sorry for the delay in answering. I managed to solve this problem by clearing some flags and fifo Rx data buffer. I also made some conditions with RTS flag.

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Pavel
NXP TechSupport
NXP TechSupport

Usually disabling RX during TX is not needed for RS485. Most application uses RS485 is half-duplex by using two wires.

 

See the Sections 23.3.1.7 and 23.4.2.3 in the LS1028A Reference Manual:

https://www.nxp.com/webapp/Download?colCode=LS1028ARM

 

These Sections contains the following:

RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.

This signal is used for switching RS485 transceiver.

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Bruno_Rodrigues485
Contributor I

Hello, thanks for your answer, but my question isn't in that sense that you understood. I will explain in more detail what I'm doing and what I really need to know. First of all, the flow control is being made through manual control of the gpio RTS pin and the behavior is being expected as shown in the image below.

Analisador_edit.png

That is, in this case, the DE of the transceiver is enabled through a GPIO of the processor and not through the RTS_B of the transmitter. 

gpio.png

Just before the transmission happens, the RTS pin is set to high logic level and, after the end of the transmission, is set to low logic level again. I did this RTS control into the driver, set to high in the function of transmission (lpuart32_transmit_buffer()) and setting to low in the event of interrupt that is called when the transmission is complete (I used the ninth bit of the LPUART Status Register [UARTSTAT_TC]).

Transmit_Buffer_edit.pngIrqreturn_edit.pnguartstat_tc.png

 

Now, I need to transmit and I don't want the reception to see what I've just transmitted. So, I tried to disable the reception just after enabling the RTS and just before starting the transmission. I enable the reception again when the transmission gets complete and just before RTS becomes disabled again. I used the thirteenth bit of the LPUART Control Register (UARTCTRL_RE) to enable and disable the reception.

Transmit_bufferEDIT.pngirqreturn__edit.pnguartctrl_re.png

The problem is when I disable the reception, the event of complete transmission doesn't occur and, consequently, RTS isn't disabled again and reception also isn't enabled. This causes no more data to be received.

Analisador_edit.png

So, what I need to do is disabling the reception while occurs a transmission. My questions are: can I work with the reception this way, directly changing the register? Why doesn't the event of transmission complete occurs when the reception is disabling? 

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Pavel
NXP TechSupport
NXP TechSupport

Is your command sequence the following?

(1). Wait setting the UARTSTAT_TC bit.

(2). Clear the GPIO_RTS bit

(3). Set the UARTCTRL_RE bit for enabling data receiving.

(4). If there are data for transmit, clear the UARTCTRL_RE bit.

(5). Set GPIO_RTS bit

(6). transmit data

(7). return to (1)

 

Is the UARTSTAT_TC bit not set if the UARTCTRL_RE bit is cleared?

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Bruno_Rodrigues485
Contributor I

Actually, the UARTSTAT_TC interrupts the processor. This is the true sequence:

(1). If there are data for transmitting, set GPIO_RTS bit

(2) Clear the UARTCTRL_RE bit. So that no more data is received.

(3). transmit data

(4). When the transmission is completed, UARTSTAT_TC is set and interruption is handled.

(5). In the interruption handler, set the UARTCTRL_RE bit for enabling data receiving.

(6) In the interruption handler, clear the GPIO_RTS bit

(7). return to (1)

Steps to perform transmission with ECHO: 1, 3, 4, 6, 7
Steps to perform transmission without ECHO: 1, 2, 3, 4, 5, 6, 7

The problem is that when step 2 is performed, step 4 will not occur.

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Pavel
NXP TechSupport
NXP TechSupport

Test your board is your command sequence is changed.

(1). If there are data for transmitting, Clear the UARTCTRL_RE bit. So that no more data is received.

(2) set GPIO_RTS bit

(3). transmit data

(4). When the transmission is completed, UARTSTAT_TC is set and interruption is handled.

(5). In the interruption handler, set the UARTCTRL_RE bit for enabling data receiving.

(6) In the interruption handler, clear the GPIO_RTS bit

(7). return to (1)

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Bruno_Rodrigues485
Contributor I

Unfortunately, your suggestion of change the sequence didn't work. 

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Pavel
NXP TechSupport
NXP TechSupport

Perhaps a delay is needed between steps 2 and 3. Also a delay is needed between steps 6 and 7.

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