Reading eTSEC3_MDIO_MIIMIND register causes "Data Abort"

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Reading eTSEC3_MDIO_MIIMIND register causes "Data Abort"

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swanandpurankar
Contributor III

Hi,

I am configuring LS1021A Tower board's TSEC3 in RGMII mode.

I am following steps mentioned in Reference manual.

I am facing strange problem that writing to MDIO_MIIMIND register is causing "Data Abort".

I am reading from address 0x2DA4534. I am reading value as *((U32*)0x2DA4534.

It generates Data abort and resets.

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1 Solution
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ufedor
NXP Employee
NXP Employee

Please note that there are two cases:
1) MDIO is used to configure external PHY - eTSEC1 MDIO must be used in this case because only EMI1_MDC and EMI1_MDIO are exposed externally.

2) MDIO is used to configure internal TBI PHY in SGMII mode - in this case MDIO of each of eTSEC1 and eTSEC2 should be used correspondingly. Note that eTSEC3 can't operate in SGMII mode, so it does not possess MDIO registers.

TBIPA defines TBI PHY address of the specific eTSEC.

For MDIO transaction PHY address (at MIIMADD[PHY_Address]) and the PHY register address (at MIIMADD[Register_Address]) are used.
The
eTSEC1 TBI PHY address (defined in the TBIPA) should NOT be equal to any external PHY address.
This means that eTSEC TBI PHY is connected to the same MDIO bus as external PHYs, so it must have different address.

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936 Views
ufedor
NXP Employee
NXP Employee

Please note that there are two cases:
1) MDIO is used to configure external PHY - eTSEC1 MDIO must be used in this case because only EMI1_MDC and EMI1_MDIO are exposed externally.

2) MDIO is used to configure internal TBI PHY in SGMII mode - in this case MDIO of each of eTSEC1 and eTSEC2 should be used correspondingly. Note that eTSEC3 can't operate in SGMII mode, so it does not possess MDIO registers.

TBIPA defines TBI PHY address of the specific eTSEC.

For MDIO transaction PHY address (at MIIMADD[PHY_Address]) and the PHY register address (at MIIMADD[Register_Address]) are used.
The
eTSEC1 TBI PHY address (defined in the TBIPA) should NOT be equal to any external PHY address.
This means that eTSEC TBI PHY is connected to the same MDIO bus as external PHYs, so it must have different address.