BL2 run next image failed

[ainolike]

According repeated tests, I found that not every time BL2 loads image successfully. It always stops at loading image. I change the DDR configuration to CONFIG_STATIC_DDR and modify the register value, this problem no longer exists. I think it is maybe the DDR configuration problem. And now I want to know how to configure DDR according to modify ddr_raw_timing parameters, especially caslat_x?

Our product has two DDR4 chips on board. The type of DDR is MT40A512M16LY-062 IT:E, and the following is my configuration.

/* DDR model number: MT40A512M16LY-062 IT:E */
struct dimm_params ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 2147483648u,
.capacity = 2147483648u,
.primary_sdram_width = 32,
.rdimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 16,
.n_col_addr = 10,
.bank_addr_bits = 0,
.bank_group_bits = 1,
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 625,
.tckmax_ps = 1500,
.caslat_x = 0x0001FFE00,
.taa_ps = 15000,
.trcd_ps = 15000,
.trp_ps = 15000,
.tras_ps = 32000,
.trc_ps = 47000,
.twr_ps = 15000,
.trfc1_ps = 350000,
.trfc2_ps = 260000,
.trfc4_ps = 160000,
.tfaw_ps = 30000,
.trrds_ps = 5300,
.trrdl_ps = 6400,
.tccdl_ps = 5000,
.refresh_rate_ps = 7800000,
.dq_mapping[0] = 0x0,
.dq_mapping[1] = 0x0,
.dq_mapping[2] = 0x0,
.dq_mapping[3] = 0x0,
.dq_mapping[4] = 0x0,
.dq_mapping_ors = 0,
.rc = 0x1f,
};

[zhuhongxian]

I have this problem。How can i solve it？

NOTICE: Fixed DDR on board

NOTICE: 1 GB DDR4, 32-bit, CL=11, ECC off
NOTICE: BL2: v1.5(release):LSDK-20.12-dirty
NOTICE: BL2: Built : 21:02:31, Feb 24 2021
NOTICE: BL2: Booting BL31

[Bulat]

Almost all mentioned parameters come directly from SDRAM data sheet.

'caslat_x' represents supported CAS latency values. For SDRAM 062E speed bin you need to set

.caslat_x = 0x02BFF800; this enables following CL settings: 10-20, 22, 24.

.dq_mapping values are defined by DQ signals routing. Values 0x0 correspond to one-to-one routing, that is MDQ0 - DQ0, MDQ1 - DQ1, MDQ2 - DQ2 etc.

Regards,

Bulat

[ainolike]

I tried as you said, but it doesn't work.  I wonder know whether every bit in 'caslat_x' corresponding to a CL value . If so, I want to confirm why bit11 corresponding to CL10  rather than bit10? 

And my DDR is not 062E, but 062.

[Bulat]

You are right, bit 10 corresponds to CL=10, so correct value for 062E is caslat_x = 0x015FFC00. As I can see in the SDRAM data sheet for 062 speed bin, supported CL settings are 10,12,14,16,18,20,24. I believe you can calculate new caslat_x now.

Regards,

Bulat

[ainolike]

With the following modification, the board boot successfully.

.caslat_x = 0x01555400,

...

.dq_mapping[0] = 0x15,

.dq_mapping[1] = 0x36,

.dq_mapping[2] = 0x02,

.dq_mapping[3] = 0x22,

.dq_mapping[4] = 0x0c,

.dq_mapping[5] = 0x2b,

.dq_mapping[6] = 0x16,

.dq_mapping[7] = 0x36,

The dq_mapping value is set according to reading the dq_mapping register in U-Boot.

Could you give me some help about dq_mapping configuration?

[Bulat · Accepted solution]

As I wrote, dq_mapping values are defined by DQ signals routing between the SDRAM and processor. Details can be found in the ref manual, see description of the DDR_DQ_MAP0 register. For example if you select .dq_mapping[0] = 0x15, it means that SDRAM's bits DQ0 is connected to processor's bit MDQ3, DQ1 -> MDQ1, DQ2 -> MDQ0, DQ3 -> MDQ2.

.dq_mapping[1] = 0x36 means following: DQ4 -> MDQ7, DQ5 -> MDQ5, DQ6 -> MDQ6, DQ7 -> MDQ4.

Regards,

Bulat

[ainolike]

I see. Thanks a lot.