QorIQ PBL: what are ALTCBARH, ALTCBARL and ALTCAR

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QorIQ PBL: what are ALTCBARH, ALTCBARL and ALTCAR

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vsiles
Senior Contributor I

In the Reference Manual of the QorIQ LS1021a, in section 8 about the Pre-Boot Loader, there are references about "ACS: Alternate Configuration Space", and ALTCBARH ALTCBARL and ALTCAR.

I can't find any information about any of these on any documentation.

I'm trying to learn about secure boot for this board and my current RCW+PBI (from NXP SDK 1.9) contains PBI instruction about updating ACS. Since I don't know what this is I am lost.

Can anyone explain what these are, or give me pointers to the relevant documentation ?

Best,

V.

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ufedor
NXP TechSupport
NXP TechSupport

The "registers (ALTCBARH, ALTCBARL, and ALTCAR)" is a "cut & paste" typo.

Correct is: "register SCFG_ALTCBAR".

Example of the PBL instruction:

09570158 00000300

this PBL instruction sets the register 0x157_0158 (SCFG_ALTCBAR) to access PCIe configuration space 0x300_0000.

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vsiles
Senior Contributor I

ufedor​ Could you explain me how the 00000300 in your example is translated to 0x0300_0000 ? It doesn't seem to be an endianess conversion. I see in the documentation that the lower byte of the register is reserved, so maybe there is some shifting performed by the PBL, but I can find a clear answer. Since I need to craft such an address, I need to be sure

Best,

Vincent

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ufedor
NXP TechSupport
NXP TechSupport

When ACS=1 the resulting address is formed as concatenation:

SCFG_ALTCBAR[0:23]SYS_ADDR[23:0]

Note that SCFG bit reverse (SCFG_SCFGREVCR) must be written 0xFFFF_FFFF as a part of initialization sequence before writing to any other SCFG register.

Here is complete sequence:

09570200 ffffffff Set 157_0200 SCFG bit reverse (SCFG_SCFGREVCR)

09570158 00000300 Set 157_0158 ALTCBAR (SCFG_ALTCBAR) to access PCIE configuration space.

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brettstahlman
Contributor III

@Fedor,

09570200 ffffffff Set 157_0200 SCFG bit reverse (SCFG_SCFGREVCR)

09570158 00000300 Set 157_0158 ALTCBAR (SCFG_ALTCBAR) to access PCIE configuration space.

What would the sequence look like for LS1012A, which doesn't have the SCFG_SCFGREVCR register?

Here is my attempt at writing the IATU_REGION_CTRL_1_OFF_INBOUND_0 register from PBL:

09570158 00000300
09610000 00000000
89400900 04000080
89400904 00000000

Does it look correct, or is something else needed to accomplish the bit swapping mentioned in the following rather vague comment in the SCFG row of Table 2-3?

Some bit fields are swapped bitwise when connected to other modules.

Thanks,

Brett S.

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vsiles
Senior Contributor I

Thank you ufedor for your reply. Is it really a concatenation ? I thought it would be a "or" or something.

So the 0000_0300 is shifted by 16 to create 0300, and then the address from followin ACS=1 instrutions are concatenated to it ?

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ufedor
NXP TechSupport
NXP TechSupport

For the 0000_0300 the SCFG_ALTCBAR[0:23] is 000003.

The concatenated 40-bit address is: 0003_SYS_ADDR[23:0]

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vsiles
Senior Contributor I

Ok, I get it now, thank you very much for all the details

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vsiles
Senior Contributor I

I think I got it, thank you !

Just to be sure (from the Refman and the info you provided):

- the PBL can only directly access the first 32 Mb of the CCSR using PBI.ACS == 0

- to access higher addresses, PBL can set the SCFG_ALTCBAR and access 32 Mb starting at this offset, using PBI.ACS == 1 instructions ?

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