QorIQ LS1021A DIFF_SYSCLK input specifications

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QorIQ LS1021A DIFF_SYSCLK input specifications

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fdm
Contributor IV

Hi,

 

Would you confirm that the DIFF_SYSCLK inputs in LS1021A and T1040 have different DC characteristics?

Both processors' datasheets describe this input as LVDS receiver with internal 100 Ohm terminator and direct coupling (Fig.11 in T1040 DS and Fig.10 in LS1021A DS).

Both processors' design checklists say: "Although it is a LVDS type clock driver but it has AC/DC characteristics identical to the SerDes reference clock inputs which are HCSL-compatible".

Preliminary revision of LS1021A datasheet and current revision of T1040 datasheet both say: "For DC timing specification, see DC-level requirement for SerDes reference clocks". These SerDes reference clock inputs have an internal AC-coupling, and consequently they can tolerate zero CM voltage in the case of an external AC-coupling.

But, in contrast, current revision of LS1021A datasheet have a separate table with DC characteristics for DIFF_SYSCLK, and the input common mode voltage of (50...1570)mV is specified.

Does LS1021A support an external AC coupling at DIFF_SYSCLK input? Should an external biasing be implemented in this case and what is the recommended schematic for the such biasing?

Does LS1021A really support DC-coupled connection of LVPECL driver (Vcm=2.0V) as it shown at Figure 27 of the Design Checklist? What should be the missing value of the R2 resistors in this case? 

 

BR,

   Denis

(P.S. There is the discussion of T1040 DIFF_SYSCLK input)

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r8070z
NXP TechSupport
NXP TechSupport

Have a great day,

Unfortunately the T1040 data sheet misguide us. I am sorry. Per answer from SOC design there is not AC coupling in the DIFF_SYSCLK clock receiver. The 100ohm termination is enabled by cfg_eng_use1 por config signal - it should be pulled high during POR for that. It was stated the specs for LVDS clock receiver have been updated and you will need to refer the T1024 data sheet for now. The T1040 data sheet will update soon. I have checked that Input differential voltage swing and common mode voltage are the same in the LS1021A and T1024 data sheets. Input common mode voltage should be in 50mV - 1570mV, input differential voltage swing should be in 100mV - 600mv. I do not think that connection shown on the Figure 27 is suitable. R2 can decrease input differential voltage swing but do not decrease common mode voltage which is ~2V  while should be < 1.57V.

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fdm
Contributor IV

Serguei,

I have the T1040 based PCB currently being at the fab that has an AC coupled CML clock driver at the DIFF_SYSCLK input w/o any biasing, and I need to know if the PCB rework required before bring-up.

Would you confirm that an external biasing is absolutely needed when using an  AC coupling?

(Upd: T1024 and T1021A design checklists both contain a note that DIFF_SYSCLK pins can be left floating if not used. Is it correct if there's no internal biasing?)

Regards,

   Denis

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r8070z
NXP TechSupport
NXP TechSupport

I’ve referred to the answer I found in our answers archive. So if we trust to it, then you should check signal on the T1040 DIFF_SYSCLK input against the DC requirements in the T1024 data sheet. Or you can create request to the design group - please see how Enter a Service Request to discuss confidential information

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