QSPI control of the WP signal to restore flash lock up

[lucroy]

We are using the ls1021iot board with the s70fl01gs nor flash on board.

The SDWD, BP0-2 bits of the status register of the s70fl01gs were inadvertently set to one and are stuck in that mode. Power cycle does not restore the flash.

The s70fl01gs document specifies the following:

If WP# signal (according to IOT schematic: LS1021 pin C12, label IFC_A24/QSPI_DIO_A2/IFC_WP3) is high the SRWD bit and BP bits may be changed by the WRR (Write Register) command.

Is it possible to control the WP# signal of the QSPI device while sending a message (WRR: Write Register) to the s70fl01gs nor flash?

[r8070z]

Have a great day,

Please see section 28.3.1 Driving External Signals in the QorIQ LS1021A Reference Manual, Rev. 1, 06/2016. It says that when the instruction is sent to the serial flash device all QSPI_DIO_A[0:3] signals are driven. In cased of Single Pad and Dual PAD Instructions QSPI_DIO_A2 is driven high.

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