QORIQ IFC address pins multiplexing in GPCM mode

[fdm]

Hi,

Is there any possibility for IFC in GPCM mode to use multiplexed ready/busy signals (e.g. IFC_RB[2:4]_B for T1040 or IFC_RB[2:3]_B for LS1021A) and, at the same time, to have access to more than 16 address LSBs (e.g. ADDR[14:31])?

BR,
   Denis

[alexander_yakov]

Yes, IFC_RB lines may be shared internally. Please see LS1021A Reference Manual, Section 23.2.1.2 "Internal connectivity of RB signal". For T1040 similar information is given in section 24.2.1.2

Have a great day,
Alexander
TIC

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[fdm]

Hi Alexander,

I am sorry if my question was not clear enough.

There is some inconsistency in the Reference manual concerning WP and RB signals - the term "signal" is used sometimes to name individual internal signals corresponding to chip selects as well as IFC block inputs/outputs (some of them are multiplexed together) and external WP and RB pins (some of them are multiplexed with e.g. GPIO).

I meant an independent (non-multiplexed) usage of more than two external IFC_RB signals (i.e. IFC_RB[0:3]_B pins) for the 22/25-bit address mode.

BR,
   Denis

[alexander_yakov]

Please look Table 3-10 in LS1021A Reference Manual. The 22/25 mode setting RCW[IFC_A_22_24] affects only address bits 22, 23 and 24. These address lines are shared with IFC_WP[1:3], so this means you can use either 22 bit and IFC_WP[1:3] or 25 bits and IFC_WP[1:3] will be not available.

IFC_RB[2,3] are shared with upper address lines IFC_A[25,26], function is selected by RCW[IFC_GRP_n_BASE]

[fdm]

Alexander,

My question is how to access these A[29:31] and/or A[26:28] address LSBs that are exposed at ADDR[25:27] and ADDR[22:24] pins and multiplexed with RB and WP.

In GPCM mode only "Mode 0 pin muxing" (CSORn[ADM_SHFT_MODE] = 0) can be used. In this case "The system address directly gets assigned to the IFC address bus (ADDR[0:31]) irrespective of the ADM_SHFT value" according to the Reference Manual.

Does it mean that in, e.g., 22-bit address mode the only way to access address LSBs is to shift these bits to the AD bus by CSORn[ADM_SHFT]=16 thus making A[4:15] address MSBs inaccessible?

BR,
   Denis

[alexander_yakov]

Yes, your understanding is correct. If particular pins are exposed, you can use these pins as address pins, and than you can use address shifting to shift particular addresses to these pins. If particular pins are not configured as address pins, but configured as RB and WP, than you can not use these pins are address pins, and therefore you have to shift addresses to currently available address lines.

[fdm]

Finally, let me summarize my understanding (e.g. for LS1021A):

There's no mechanism that internally remaps address LSBs at ADDR[ ] pins in 25-bit and 22-bit address mode as compared to 28-bit mode when ADM_SHFT_MODE = 0 irrespective of the IFC-related RCW settings and, as a consequence, there's no possibility to use all these 25-bit and 22-bit addresses as a continuous address space in GPCM mode.

Am I right?

[alexander_yakov]

No, this is not quite correct. Internal ADM_SHIFT mechanism is completely unrelated to number of externally exposed pins, this is done by different device blocks.

[fdm]

Would you please clarify which part of my statements is not quite correct in the context of my initial question?