Problem with LS1088a and DDR4 without ECC on own board

[radoslawadamczy]

Hello,
We design own board with LS1088A Processor and DDR4 inhouse (Four chips MT40A512M16JY-083E:B 0  - no ECC).
I use LSDK 19.06 to make firmware.

My problem is with DDR controller that won't to train write_leveling with any settings clk_adj and wl_start),

I get error:
Found training error(s): 0x3102 or 0x2001 (What that means?)
ERROR:   Writing DDR register(s) failed
ERROR:   Programming DDRC error
ERROR:   DDR init failed

And debug registers are:
VERBOSE: Reading debug[9] as 0x10101010
VERBOSE: Reading debug[10] as 0x10101010
VERBOSE: Reading debug[11] as 0x10101010
VERBOSE: Reading debug[12] as 0x10101010

Training errors is dump from debug[1] register.

Anybody can explain us what is description of debug registers 1, 9, 10,11 and 12?

Anybody have suggestions what maybe wrong in DDR controller configuration?

We have checked:
1. Check list to design according to suggestions of AMF-NET-T3267 document,
2. DDR clock,
3. Voltage,
4. Reset lines

Registers DDR controller dumps:

VERBOSE: Parse DIMM SPD(s)
VERBOSE: cal cs
VERBOSE: cs_in_use = 1
VERBOSE: cs_on_dimm[0] = 1
NOTICE:  Fixed DDR on board
INFO:    Time after parsing SPD 14 ms
VERBOSE: Synthesize configurations
VERBOSE: cs 0
VERBOSE:      odt_rd_cfg 0x0
VERBOSE:      odt_wr_cfg 0x4
VERBOSE:      odt_rtt_norm 0x3
VERBOSE:      odt_rtt_wr 0x4
VERBOSE:      auto_precharge 1
VERBOSE: ctlr_init_ecc 0
VERBOSE: x4_en 0
VERBOSE: ap_en 0
VERBOSE: ctlr_intlv 0
VERBOSE: ctlr_intlv_mode 0
VERBOSE: ba_intlv 0x0
VERBOSE: data_bus_used 0
VERBOSE: otf_burst_chop_en 1
VERBOSE: burst_length 0x6
VERBOSE: dbw_cap_shift 0
VERBOSE: Assign binding addresses
VERBOSE: ctlr_intlv 0
VERBOSE: rank density 0x100000000
VERBOSE: CS 0
VERBOSE:     base_addr 0x0
VERBOSE:     size 0x100000000
VERBOSE: base 0x0
VERBOSE: Total mem by assignment is 0x100000000
VERBOSE: Calculate controller registers
VERBOSE: Skip CL mask for this speed 0x400
VERBOSE: Skip caslat 0x400
VERBOSE: cs_in_use = 0x1
VERBOSE: cs0
VERBOSE:    _config = 0x80840412
VERBOSE: cs[0].bnds = 0xff
VERBOSE: sdram_cfg[0] = 0xc5000008
VERBOSE: sdram_cfg[1] = 0x401150
VERBOSE: sdram_cfg[2] = 0x0
VERBOSE: timing_cfg[0] = 0x91550018
VERBOSE: timing_cfg[1] = 0xbac48e54
VERBOSE: timing_cfg[2] = 0x490118
VERBOSE: timing_cfg[3] = 0x10c1000
VERBOSE: timing_cfg[4] = 0x220002
VERBOSE: timing_cfg[5] = 0x3401400
VERBOSE: timing_cfg[6] = 0x0
VERBOSE: timing_cfg[7] = 0x13300000
VERBOSE: timing_cfg[8] = 0x2336800
VERBOSE: timing_cfg[9] = 0x0
VERBOSE: dq_map[0] = 0x7053658
VERBOSE: dq_map[1] = 0xd10d0ed8
VERBOSE: dq_map[2] = 0x3b407700
VERBOSE: dq_map[3] = 0xed0000
VERBOSE: sdram_mode[0] = 0x3030211
VERBOSE: sdram_mode[1] = 0x8000000
VERBOSE: sdram_mode[9] = 0x4000000
VERBOSE: sdram_mode[8] = 0x500
VERBOSE: interval = 0x18600000
VERBOSE: zq_cntl = 0x8a090705
VERBOSE: ddr_sr_cntr = 0x0
VERBOSE: clk_cntl = 0x1c00000
VERBOSE: cdr[0] = 0x80040000
VERBOSE: cdr[1] = 0x8d81
VERBOSE: wrlvl_cntl[0] = 0x86750609
VERBOSE: wrlvl_cntl[1] = 0x9090909
VERBOSE: wrlvl_cntl[2] = 0x9090909
VERBOSE: debug[28] = 0x37
INFO:    Time before programming controller 184 ms
VERBOSE: Program controller registers
INFO:    ddrc version: 00050201
VERBOSE: sdram_cfg_2 0x00401150
VERBOSE: wrlvl_cntl[0] 0xc6750609
VERBOSE: total size 4 GB
VERBOSE: Need to wait up to 1320 ms
VERBOSE: Reading debug[9] as 0x10101010
VERBOSE: Reading debug[10] as 0x10101010
VERBOSE: Reading debug[11] as 0x10101010
VERBOSE: Reading debug[12] as 0x10101010
VERBOSE: cpo_min 0x10
VERBOSE: cpo_max 0x10
VERBOSE: debug[28] 0x700037
VERBOSE: Optimal cpo_sample 0x37
VERBOSE: Err_detect 0x80
ERROR:   Found training error(s): 0x3102
ERROR:   Writing DDR register(s) failed
ERROR:   Programing DDRC error
ERROR:   DDR init failed.

Thanks

[yipingwang]

Please check whether register DDR_ERR_DETECT[ACE] is set, if yes, please check the following probable reason.

1. The training sequence that the controller follows to calibrate the read data path was not able to complete. This would probably only happen if there was a hard failure on the memory interface caused by board-level issues or incorrect controller settings.

2. Incorrect termination of MDICx signals.

3. Write leveling calibration was not able to complete. This relates to improper settings of the DDR_WRLVL_CNTL register or board-level issues.

In addition, I suggest you use QCVS DDRv tool to do DDR configuration optimization and validation.

[radoslawadamczy]

Hello Yiping Wang,

Thanks for answer,

Unfortunately DDR_ERR_DETECT[ACE] is set.

I've checked termination of MDICx, and ZQ impedance signals and they're correct.

I'm using the  QCVS DDRv tool and only one(first) test is passed (Auto search & detect for write leveling start values). The Second test (determine the best clock adjust value) is failed - all values are red.

After, that failed calibration, when I run software memory test I get:

em error @ 0x80000100(size =8): found FFFFFFFFFFFFFFFF, expected 5555555555555555
Mem error @ 0x80000108(size =8): found FFFFFFFFFFFFFFFF, expected 5555555555555556
Mem error @ 0x80000110(size =8): found 5555555555555558, expected 5555555555555557
Mem error @ 0x80000118(size =8): found 5555555555555555, expected 5555555555555558
Mem error @ 0x80000120(size =8): found FFFFFFFFFFFFFFFF, expected 5555555555555559
Mem error @ 0x80000128(size =8): found FFFFFFFFFFFFFFFF, expected 555555555555555A
Mem error @ 0x80000130(size =8): found 555555555555555C, expected 555555555555555B
Mem error @ 0x80000138(size =8): found 5555555555555559, expected 555555555555555C
Mem error @ 0x80000140(size =8): found FFFFFFFFFFFFFFFF, expected 555555555555555D
Mem error @ 0x80000148(size =8): found FFFFFFFFFFFFFFFF, expected 555555555555555E
Mem error @ 0x80000150(size =8): found 5555555555555560, expected 555555555555555F
Mem error @ 0x80000158(size =8): found 555555555555555D, expected 5555555555555560
Mem error @ 0x80000160(size =8): found FFFFFFFFFFFFFFFF, expected 55555555555555

Any suggestion, what can be wrong?

[yipingwang]

Please refer to the following check list.

Generate the setting via QCVS:
   Use SPD if available, otherwise Auto generation and configure the properties panel according to DDR data sheet
   Select the DDR data rate based on the measured output clock
RCW needs to be valid and correct
Enter MCK to DQS skews in the DDR wizard
Verify the DQn_MAP registers are correct
Verify all related errata are implemented