Problem activating GPIO on LS1046a from PBI. Suggestions?

[AbelianMeme]

Hi everyone,

I am trying to activate a GPIO pin with PBI. I think I have setup the pin muxing correctly, but I see no activity on the output. The pins I am trying to drive high are: GPIO2_13, GPIO2_14, and GPIO4_1.

I set IFC_GRP_D_BASE=1 and IFC_GRP_D_EXT=0 in RCW for the GPIO2 pins, and EM2=1 for the GPIO4 pin.

I then set the GPIO registers with PBI. But I never see the GPIO pins being driven on the scope. Below is the .rcw file I am using. Is there something else I need to do in order to get this working?

Thank you for any assistance.

P.S. I find the reversed bit notation in the datasheet extremely confusing, so I am just tying to set the entire port high at the moment. I will figure out the specific bits later, but if anyone would like to save me the trouble I would appreciate that as well.

----------------------------------------

#include <ls1046a.rcwi>

%littleendian64b=1
%dont64bswapcrc=1

SYS_PLL_RAT=6
MEM_PLL_RAT=21
CGA_PLL1_RAT=16
CGA_PLL2_RAT=14
SRDS_PLL_PD_S1=3
SRDS_PLL_PD_S2=3
SRDS_PRTCL_S1=0
SRDS_PRTCL_S2=0
SRDS_PLL_REF_CLK_SEL_S1=0
SRDS_PLL_REF_CLK_SEL_S2=0
SRDS_DIV_PEX_S1=0
SRDS_DIV_PEX_S2=0
DDR_FDBK_MULT=2
DDR_REFCLK_SEL=0
PBI_src=4
IFC_MODE=37
HWA_CGA_M1_CLK_SEL=6
DRAM_LAT=1
SPI_EXT=1
UART_BASE=7
IFC_GRP_A_EXT=1
IFC_GRP_D_BASE=1
IFC_GRP_D_EXT=0
IFC_GRP_E1_EXT=1
IFC_GRP_F_EXT=1
IRQ_OUT=1
TVDD_VSEL=1
DVDD_VSEL=2
EVDD_VSEL=2
IIC2_EXT=1
SYSCLK_FREQ=600
HWA_CGA_M2_CLK_SEL=1
EM2=1

/* Set BOOTLOCPTR to 0x4010000 and SPI bus to 20 MHz */

.pbi
write 0x570600, 0x00000000
write 0x570604, 0x40100000
write 0x57015C, 0x10100000
.end

#include <cci_barrier_disable.rcw>

/*
Set ALTCBAR to 0x0200
Set register: @0 = '1' output, @4 = '0' to disable open drain, @8 = '1' high
GPIO2 base addr = 0x231_0000h
GPIO4 base addr = 0x233_0000h
*/

.pbi
write 0x570158, 0x00000200
flush
awrite 0x310000, 0xffffffff
awrite 0x310004, 0x00000000
awrite 0x310008, 0xffffffff
awrite 0x330000, 0xffffffff
awrite 0x330004, 0x00000000
awrite 0x330008, 0xffffffff
.end

#include <qspi_endianness.rcw>

[AbelianMeme]

A follow on to this. We are using QSPI for the RCW source. Footnote (2) on p. 214, Table 4-9, section 4.4.5.1 "Reset configuration word (RCW) source" in Rev. 3 8/2021 of the LS1046A Reference Manual states the following:

Booting from qSPI takes precedence over RCW pin multiplexing which means that QSPI_A_DATA[0:3], QSPI_A_CS0, QSPI_A_CS1, QSPI_A_SCK, QSPI_B_CS0,QSPI_B_CS1, QSPI_B_SCK are used regardless of RCW setting.

We are only using QSPI_A, and QSPI_B_DATA[0:3] are not listed as prohibited pins on the above note. However, it is possible there is an error in the manual, and that QSPI_B_DATA[0:3] are also unavailable? GPIO2_13 and GPIO2_14 share pins with QSPI_B_DATA0 and QSPI_B_DATA1. So 3 possible questions.

1) Is the reference manual wrong, and QSPI_B_DATA[0:3] also blocked when using QSPI as the RCW source?

2) If (1) is true, can I reconfigure the pin mux to recover the functionality of QSPI_B_DATA[0:3] after bootup? If so, how?

3) In any case, the original question still stands about GPIO4, which is activated by EM2=1, and would be unaffected by the above issue.

[ufedor]

1) No.

Please provide binary image of the resulting RCW+PBI.