PHY-LS1088A SerDes link not coming up

[slakhal]

We have an issue with the LS1088A SerDes link between the processor and a set of Microsemi VSC8562/VSC8564 PHY transceivers.

The RCW is configured to use protocol 54 as outlined:

SRDS_PRTCL_S1_LN0=0b0011
SRDS_PRTCL_S1_LN1=0b0011
SRDS_PRTCL_S1_LN2=0b0100
SRDS_PRTCL_S1_LN3=0b0100

VSC8562 is connected to lanes C and D. Two VSC8564 are connected to lanes A and B.

Our board runs U-Boot and Linux. We don't have any custom code that writes the SerDes registers.

What we observed is that the PHYs are correctly configured by their drivers through the MDIO interface.
The Ethernet link comes up and we can see that by reading the PHY registers in U-Boot. Linux sees the link and sets the appropriate speed for it. There are no packets flowing through the link.
When we check the SerDes link status on the PHYs, it never comes up.

Is there a setting to set or read in any of the SerDes registers that can help diagnose the problem?

Thanks for any feedback,
Samir.

[SebastianG]

hello @slakhal,

I would like to inform you that I'm working on your question, I will let you know as soon as I have an update.

Thank you so much for your patience

Regards,

Sebastian

[slakhal]

Hi Sebastian,

I forgot to mention that we have tested the link in loopback by setting LNCTCSR3 SerDes register. That was in U-Boot. Ping data were sent and received as expected.

Thanks,

Samir 

[SebastianG]

Hello @slakhal ,

Could you please share with me the following details:

• The log with the steps that you use for SerDes link up and the outputs
• Which SerDes protocols are you using?
• Dump registers of SerDes

Regards,

Sebastian

[slakhal · Accepted solution]

Hi Sebastian,

The protocol used on our board is 54, which is "3,3,4,4" (RCW SRDS_PRTCL_S1_LN0 to SRDS_PRTCL_S1_LN3).

+============+==========+=================+
| Lane | SGn/QSGx | MAC |
+============+==========+=================+
| lane 0 (D) | SG2 | MAC 2 |
| lane 1 (C) | SG1 | MAC 1 |
| lane 2 (B) | QSGb | MAC 7 to MAC 10 |
| lane 3 (A) | QSGa | MAC 3 to MAC 6 |
+============+==========+=================+

We created U-Boot scripts to dump SerDes and PHY registers. These little scripts were themselves created from a spreadsheet that contained the register definitions.

The scripts and the results/output are in the attached serdes-phy-steps-logs.txt. I also attached SerDes.pdf, which contains a human-readable view of the SerDes and PHY settings when SerDes and PHY were not talking on the SerDes interface.

Looking at SerDes.pdf, Link status of PHY Mode Status register is 1 (up). SerDes signal detect of PHY MAC SerDes status is 0 (SerDes signal detection did not occur). This indicates that 10xxBASE-T interface was up (cable connected) but SerDes SGMII was down between PHY and the processor.

To fix our issue, we modified MAC SerDes autonegotiation enable of PHY MAC SerDes PCS Control 16E3 register to 1 (MAC SerDes ANEG enabled.) We did not dump the registers in this case. Testing proved that the board Ethernet was working in Linux after boot.

Thanks and best regards,

Samir

[slakhal]

Hi Sebastian,

We finally got the VSC856x PHYs to talk to LS1088A via SerDes. We had to modify MSCC driver in U-Boot to enable auto-negotiation on the MAC SerDes interface. Prior to that, we had to add support for these PHYs in U-Boot.

Thank you for your support and time,

Samir