In STANDBYWFI (PW15) state, the core internally gates clocks within the core,
significantly reducing the power consumption of the core. Snooping of the L1 and L2 are still supported and thus the data in the data cache is kept coherent. Interrupts directed to the Core are monitored by the GIC and cause core to exit from STANDBYWFI (PW15) state to allow the core to recognize and process the interrupt. STANDBYWFI (PW15) state is entered through execution of wait for interrupt instruction from the core.
The watchdog timer facilities are still enabled during STANDBYWFI (PW15) state.
Core PH20 state is core power gating with state retention.
• Entry into PW15 mode core power management state via wait for interrupt
instruction execution by the core
• Entry into PH20 core power management state via RCPM PCPH20SETR for
request to enter the core's PH20 state.
Please refer to "13.1.3.1 Power Management State Summary " in LS1046ARM.pdf.