PCIe ERR_FATAL interrupt on LS1043A

[kunal_b]

Hi,

On LS1043A, I am using PEX3 controller to make a PCIe link to an endpoint device. I am trying to generate an interrupt to GIC if Root Complex (in LS1043A) receives ERR_FATAL error message. LS1043A RM section 28.6.1.8.2 RC Inbound Messages mentions that this is possible. I think section 28.1.1 MSI Implementation is useful to generate the interrupt but I am not able to understand how to use the SCFG registers mentioned in that section.

What SCFG register settings do I need to configure to get GIC interrupt when PEX3 Root Complex receives ERR_FATAL error message? What is the interrupt number of that interrupt? 

I am using PCIe Base Spec 3.0 section 6.2.6 Error Message Controls as a guide for PCIe register settings to enable error reporting.  

Thank you

[JosephAtNXP]

Hi, Kunal

If you want to test that interrupt when no ERR_F message is received, IBS and SRS bits need to be written, they will trigger the interrupt.

The interrupt number is in 28.1.1 Table, in the rightmost part of the table, just above the arrows.

Consider that the interrupts for the MSI are handled by the SCFG.

Best regards, Joseph Linares

[kunal_b]

Hi Joseph

A couple of questions-

1) I don’t want to simulate the PCIe interrupts, but good to know that I can simulate the interrupt by writing IBS and SRS bits of SCFG registers. For PEX3, which interrupt number should be used to get interrupt on ERR_FATAL message? My assumption is that I cannot randomly pick one of the 12 interrupts mentioned in LS1043A RM section 28.1.1.

2)  I know that LS1043A RM section 12.3.55 to 12.3.69 are interrupt settings but I do not understand writing to which of those register will enable interrupt for ERR_FATAL message. It will really help if you can tell me what value to write in which SCFG registers. 

From PCIe Base Spec 3.0 and LS1043A RM, I think I have figured out PCIe register settings to enable fatal error reporting, but I am confused about SCFG settings to enable PCIe ERR_FATAL interrupt. Answering above 2 questions will help me understand.

Thank you

-Kunal

[JosephAtNXP]

Hi, sorry for the delay, I've almost just been notified.

1. The group index register is responsible for triggering four interrupts, you will not get random interrupts. Writing to one of the three group registers will reduce the 12 possibilities to 4 of them.

The second bit-group will determine which interrupt will be triggered, for example in the group 0: SCFG_G0MSIRn.

This is why I believe that writing to that register will trigger the interrupt, and I understand that the MSI address of the message has to point to this group register.

2. Should be already covered by the last point.

Best regards,