Hi,
I am using NXP layer scale chipset LS1046A for our new 5G small cell product. I am seeing power consumption of the chip on VDD 1V rail would be around 16 to 20W at 1800MHz operation, which is an extremely high number for our application. Our complete product's power boundary would be within 35W. As a way of optimizing power, we tried to work with datasheet details on core utilization and thyrstone activity factors rate of 70%, 100%, 115%, but we end up clueless on how to handle these details based on utilized resources. It is the place where we are looking for support and guidance on how much exact power would be consumed by the chip based on the resources we utilize.
Resources used:
1) DDR4 controller: dual-rank DIMM DDR4 module at 2100 MHz rate is planned.
2) SERDES1: 10G XFI- planned for SFP port
3) SERDES2: PCIe gen3-4 lanes for baseband processor communication
4) RGMII: 1G RJ45- copper Ethernet plus PoE++
5) QSPI: 16Gb NOR flash
6)16GB EMMC
7) IFC: CPLD of 146 balls for power sequencing and control
1PPS synced clocks for system ref clocks, DDR clocks, etc. are provided to the chip.
This is the overall system architecture. Still, at this time we don't know whether this system must require max. core freq. of 1800MHz for our application. or if we go with 1200, 1400 MHz as well, is it still works well?? Also, we have followed the reference schematic of NXP eval board LS1046ARDB-PB using the same processor.
Anybody can help me in calculating optimized power consumption for VDD core rail here..? or any power consumption calculation worksheet available for this VDD rail..? Please help.
Regards,
Pradeep. S
