HI @andrei_skok
it seems I have no permission reply in case, so I reply here.
- The version of MC as below:
U-Boot 2019.10 (Oct 12 2021 - 11:09:54 +0800)
SoC: unknown (0x87361020)
Clock Configuration:
CPU0(A72):2200 MHz CPU1(A72):2200 MHz CPU2(A72):2200 MHz
CPU3(A72):2200 MHz CPU4(A72):2200 MHz CPU5(A72):2200 MHz
CPU6(A72):2200 MHz CPU7(A72):2200 MHz CPU8(A72):2200 MHz
CPU9(A72):2200 MHz CPU10(A72):2200 MHz CPU11(A72):2200 MHz
CPU12(A72):2200 MHz CPU13(A72):2200 MHz CPU14(A72):2200 MHz
CPU15(A72):2200 MHz
Bus: 750 MHz DDR: 3200 MT/s
Reset Configuration Word (RCW):
00000000: 5883833c 24580058 00000000 00000000
00000010: 00000000 0c010000 00000000 00000000
00000020: 016001a0 00002580 00000000 1800164e
00000030: 08000000 00000000 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027088 00000000
00000070: 00b30030 00150022
Model: NXP Layerscape LX2160ARDB Board
Board: unknown-RDB, Board version: @, boot from eMMC
FPGA: v0.0
SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz
SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz
VID: failed to select VDD Page 0
VID: Couldn't read sensor abort VID adjustment
core voltage not adjusted
DRAM: 15.9 GiB
DDR 15.9 GiB (DDR4, 64-bit, CL=22, ECC off)
Using SERDES1 Protocol: 19 (0x13)
Using SERDES2 Protocol: 5 (0x5)
Using SERDES3 Protocol: 0 (0x0)
SERDES3[PRTCL] = 0x0 is not valid
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
EEPROM: Read failed.
In: serial_pl01x
Out: serial_pl01x
Err: serial_pl01x
Net: PCA: failed to select proper channel
Could not get PHY for FSL_MDIO0: addr 4
Failed to connect
Could not get PHY for FSL_MDIO0: addr 1
Failed to connect
Could not get PHY for FSL_MDIO0: addr 2
Failed to connect
PCIe0: pcie@3400000 disabled
PCIe1: pcie@3500000 disabled
PCIe2: pcie@3600000 Root Complex: no link
PCIe3: pcie@3700000 disabled
PCIe4: pcie@3800000 disabled
PCIe5: pcie@3900000 disabled
DPMAC3@xgmii
Warning: DPMAC3@xgmii (eth0) using random MAC address - ce:b2:70:e8:0e:71
, DPMAC4@xgmii
Warning: DPMAC4@xgmii (eth1) using random MAC address - b2:34:6b:97:5e:dc
, DPMAC5@25g-aui
Warning: DPMAC5@25g-aui (eth2) using random MAC address - de:c6:89:80:14:f6
, DPMAC6@25g-aui
Warning: DPMAC6@25g-aui (eth3) using random MAC address - be:33:ec:55:16:59
switch to partitions #0, OK
mmc1(part 0) is current device
MMC read: dev # 1, block # 20480, count 4608 ... 4608 blocks read: OK
MMC read: dev # 1, block # 28672, count 2048 ... 2048 blocks read: OK
crc32+
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 10.20.4, boot status: 0x1)
Hit any key to stop autoboot: 0
- We use LSDK2012.
- Yes, this issue happened to both TCP and UDP traffic.
- Our Lx2160 HW board use 2.5 G PHY ethernet port, ipsec connection as below,
=>Lx2160 <------->Router<-------->Internet<--------> Security Gateway
# ipsec.conf - strongSwan IPsec configuration file
# basic configuration
config setup
# strictcrlpolicy=yes
# uniqueids = no
strictcrlpolicy=no
conn %default
# automatically generated by tenpin
keyingtries=0
dpdaction=clear
dpddelay=120s
auto=start
keyexchange=ikev2
reauth=no
mobike=no
rekeymargin=1m
ikelifetime=24h
keylife=10h
leftupdown=/usr/local/bin/gnb/ASK/ipsecScript/updown.tenpin
replay_window=64
conn conn-1
keyexchange=ikev2
ike=aes128-sha1-modp1024
esp=aes128-sha1
right=211.xx.xx.xx
leftid="xxxxxxxxxxxx.askey.com.tw"
rightid=%any
leftcert=sc.crt.pem
leftsendcert=if-asked
authby=pubkey
leftdns=%config
rightsubnet="172.29.0.0/22"
left=%defaultroute
leftsourceip=%config
leftdns=%config
fragmentation=yes
leftikeport=500
rightikeport=500
type=tunnel
- iperf3 test command as below:
=>iperf3 -c 172.29.0.x -t 60000 -R -i 10 -P8 -p 52xx
- This issue is happened when GRO is enabled.
If you need more information, please let me know.
BR,
Jack