LX2160A Serdes configuration table

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LX2160A Serdes configuration table

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jhkim2
Contributor III

I'm trying to understand initialization sequence of lx2160a serdes1.

I found the serdes configuration table in u-boot (.../arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c)

But, the lane protocol sequence of u-boot serdes1_cfg_table for serdes protocol #19 is reversed compared with the manual (QorIQ LX2160A Reference Manual, Rev. 0, 07/2020, p.1902).

For example, the lane0 protocol is USXGMII/XFI.3 in manual, but 40GE2 in u-boot sedes1_cfg_tbl[].

Could you tell me the reason?

 

Thanks in advance.

J.Hwan Kim

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yipingwang
NXP TechSupport
NXP TechSupport

Please download the latest LX2160A Reference manual from https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/la... please refer to page 1901, serdes1_cfg_tbl definition in ./arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c in u-boot source code is from Serdes1  lane A to lane H(lane7 to lane0).

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