LX2160 PCIe Compliance Testing

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LX2160 PCIe Compliance Testing

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HW_Team
Contributor I

Hi

We are undertaking PCIe physical layer compliance testing on an LX2160, we are able to interface the PCIe interface (as RC) to a Gen3 device (EP) and communicate at Gen3 speeds however we aren't able to force the link to Gen3 during compliance testing.

During compliance testing we are only able to get Gen1 and Gen2 working for RX/TX, we will attempt forcing the links using the Link Control 2 Register in the PCI RC.  Reading the link capabilities register returns that Gen1, Gen2 and Gen3 are all supported however the Link Control 2 register shows only Gen1 and Gen2.

As a further update we have attempted setting the link control 2 register for Gen1, Gen2 and Gen3 and set the compliance bit however doing so meant the link only stayed at Gen1.

To do this we set the the link control 2 register to 0x0017, compliance bit set and bits 0..2 set high for Gen1..Gen3, at reset the link control 2 register reads as 0x0003.

The testing is being performed using the PCISIG Compliance Base Board (CBB) and we are interfacing to LX2160 SERDES 3[0..3] with a PCIe Gen3 M.2 interface, the first Gen1 and Gen2 toggles on the CBB are working, moving to the Gen3 toggle doesn't change to Gen3 as expected.  Our PCIe interface does not use lane reversal or polarity inversion. 

Would you please provide the correct sequence/register settings for entering PCIe Gen3 compliance with this setup so we can proceed with the compliance testing.  The system is running Linux and we are able to modify the registers if required.

Additionally, for the PCIe receiver test, we need to allow for far-end retimed loopback training...which is the standard loopback used for PCIe RX testing, so if additional setup is required for this to work please advise.

Thanks

Malcolm

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ufedor
NXP Employee
NXP Employee

The issue investigation will be convenient to perform as a Technical Case.

Please create a Case and attach all relevant documents:

https://support.nxp.com/s/

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