LS1046ARDB, disable SPD/I2C on DDR4 SODIMM, memory timing data?

pgcordell · ‎11-02-2020

I'm running an LS1046ARDB board with DDR4 memory that does not support I2C/SPD. I am comfortable with C but this is my first experience writing code that runs this close to the hardware, so I'm on shaky ground.

I'm trying to get the board/memory combination to boot using a clone of U-Boot from https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot.git.

Here's what I get booting U-Boot without any changes.

U-Boot SPL 2018.03 (Oct 05 2020 - 20:59:36 +0000)
Initializing DDR....using SPD
DDR: failed to read SPD from address 81
Error: No valid SPD detected.

I found a solution for disabling SPD for memory for the LS1043ARDB board and tried that out. It didn't totally work. Here's what I tried.

In file include/configs/ls1046ardb.h:

add
#define CONFIG_SYS_DDR_RAW_TIMING 1

comment out
#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0

It also looked like there were memory settings/timings/etc. that needed to exist for the specific memory/hw combination. Again, I turned to the LS1043ARDB and used samples I found there just to see how far I could get. I copied the ddr_cfg_regs_1600 structure from board/freeway/ls1043ardb/ddr.h into board/freeway/ls1046ardb/ddr.h

I also added #define DEBUG into include/common.h and loaded a few debug statements into board/freeway/ls1046ardb/ddr.c

Here's the output from the serial console as a result.

U-Boot SPL 2018.03-dirty (Oct 30 2020 - 16:26:59 -0700)
CONFIG_SYS_DDR_RAW_TIMING defined
CONFIG_SPL defined
CONFIG_SPL_BUILD defined
Initializing DDR.... fsl_ddr_sdram()
starting at step 1 (STEP_GET_SPD)
Filling dimm parameters from board specific file
Computing lowest common DIMM parameters for memctl=0
lowest_common_spd_caslat is 0xf
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 938
trcd_ps = 13500
trp_ps = 13500
tras_ps = 33000
trfc1_ps = 260000
trfc2_ps = 160000
trfc4_ps = 110000
trrds_ps = 3700
trrdl_ps = 5300
tccdl_ps = 5355
trfc_slr_ps = 0
twr_ps = 15000
trc_ps = 46500
Reloading memory controller configuration options for memctl=0
WARNING: Calling __hwconfig without a buffer and before environment is ready
mclk_ps = 952 ps
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
DIMM is not supported by this board
resetting ...

So... it looks like it's getting further, but there's clearly problems. Here are my questions.

#1 Am I going about this totally the wrong way?

#2 Am I disabling SPD for the ls1046ardb correct?

#3 If the memory settings for ls1046ardb and ls1043ardb are not the same, how do I get the correct settings for ls1046ardb? I've looked
at the datasheet for the SODIMM itself (Micron MT40A1G16KNR) and don't find any numbers that look like those in the structure. Is there
a way to generate them?

#4 What am I not seeing?

yipingwang · ‎11-04-2020

Please use DDR initialization method provided in board/freescale/ls1043ardb/ddr.c.

a. Please refer to the attached description of Mock DIMM parameters, please fill "ddr_raw_timing" array in board/freescale/ls1043ardb/ddr.c according to your DDR data sheet, then build u-boot and program u-boot to NOR flash and boot up the target board. You need to define CONFIG_SYS_DDR_RAW_TIMING if using this approach.

b. In CodeWarrior IDE, please create an QCVS DDR project with "reading from target" option in DDR configuration panel.

c. In QCVS DDR project, please click "Validation" to use DDRv tool to do DDR validation and optimization.

d. After validation with DDRv tool, please generate output file from Project->Generate Processor Expert code. And please refer to "uboot_ddr1.c" file to fill "ddr_cfg_regs_1600" in board/freescale/ls1043ardb/ddr.h. You need to undefine CONFIG_SYS_DDR_RAW_TIMING when using this method.