LS1046A watchdog timeout

[zy_mooncity]

Hi folks,

I'm Writing driver for ls1046 watchdog timer for VxWorks. I setup the watch dog 1 as the step:

    val = CSR_READ_2 (pDrvCtrl, WDOG_WCR);
    val &= ~WDOG_WCR_WT_MASK;                            /* 1. clear the old time out */
    val &= (UINT16)(~(WDOG_WCR_WDE));                  /* 2. disable watch dog */
    val |= (UINT16)WDOG_SEC_TO_COUNT(peroid);    /* 3. set time out */
    CSR_WRITE_2 (pDrvCtrl, WDOG_WCR, val);
    
    val |= (UINT16)(WDOG_WCR_WDE);                       /* 4. enable watch dog */
    CSR_WRITE_2 (pDrvCtrl, WDOG_WCR, val);

([WDOG1] bit in DEVDISR5 register is set to 0 to enable watch dog 1 module before I set the watch dog)

I set 2s timeout in the WCR register and did not feed the watch dog, and I could see 2s timeout and the [WDE] bit was set successfully. After 2s or longer, I checked the Watchdog Reset Status Register (WRSR) to see the reset information. I did not see the [TOUT] bit is set.

If I set [SRS] bit in WCR register, I could see the [SFTW] bit in WRSR register was set.

Seems that the watch dog time out does not work. Any hint? Thanks.

Regards

Yun

[ufedor]

Two points to consider:

1) The core WDOG timers expiry signals are used to raise reset request to external world (RESET_REQ_B output of the SoC). Is the RESET_REQ_B assertion properly handled?

2) Refer to the LSDK watchdog driver to doublecheck the initialization settings:

imx2_wdt.c\watchdog\drivers - qoriq-components/linux - Linux Tree for QorIQ support 

[imurillo_s]

Hello,

I have a simmilar problem. I am trying to use the WD over uboot, just to check its functionality.When I activate the watchdog, It reset our board but the WDOGx_WRSR register does not change (its status is 0010h after WD reset). The commands that I use in uboot are:

mw.b 0x2A70000 0x4 1

mw.b 0x2A70001 0x34 1

## the board resets after the 2.5s

md.b 0x2A70004 2

## the output is 0010h

I have check with the HW departement and the RESET_REQ_B assertion properly handled.

Also, if I set [SRS] bit in WCR register, I could not see the [SFTW] bit in WRSR register as set.

Thank you very much.

[zy_mooncity]

Hi ufedor,

Thank you for the reply. I'm asking the hardware engineer to check the hardware design.

I found that there are two statements in Ls0146ARM "all WDOG modules use 32 KHz clock, driven at device input RTC pin for their counters (section 35.1) " and "the low frequency reference clock is a free-running clock and can't be gated (section 35.2)".

Is that to say there is no to enable WDOG_n gate clock in Device Disable Register 5 (DEVDISR5)? Just a valid RTC is enough, am I right?

Thanks and Regards.

Yun

[ufedor]

Please consider that DEVDISR5 is not about the clock, but about the modules disabling.

IP Blocks disabled by setting the corresponding bit in the DEVDISR5 register must not be re-enabled.