LS1046A custom board: what are correct DDR4 DQ pin mappings?

[valokuvaaja]

Hello everyone,

We've designed a custom board based on the LS1046A CPU using five MT40A512M16TB-062E IT:R DDR4 SDRAM chips (4 data chips + 1 ECC chip), without an SPD EEPROM on the board.

Currently, we're facing issues validating DDR memory with CodeWarrior: the DDR initialization fails during the first test ("Auto search & detect for write leveling start values") in the QCVS tool under the "Centering the clock" scenario.
The logs show the same output for `wrlvl_searcher` that is seen in the post:
DDR read/write issues custom board LS1046A 

Our main suspect is incorrect DDR DQ pins mapping.

Attached are screenshots from our board schematic:
- D16A shows one of the SDRAM chips.
- D21A shows a fragment of the DDR controller in the LS1046A.

Please focus on pins DQ0–DQ15 and associated DDR_DQxx nets.

Based on "Table 15-6. Bitfield settings for each byte lane" in the LS1046A Reference Manual, our current assumption for correct mapping is:

DQ[0:3] = [3,0,2,1] (0x14)
DQ[4:7] = [7,4,6,5] (0x34)
DQ[8:11] = [3,0,2,1] (0x14)
DQ[12:15] = [7,4,6,5] (0x34)

Is this mapping correct, or should it instead look like this?

DQ[0:3] = [1,3,2,0] (0x0C)
DQ[4:7] = [5,7,6,4] (0x2C)
DQ[8:11] = [1,3,2,0] (0x0C)
DQ[12:15] = [5,7,6,4] (0x2C)

Any advice or confirmation would be greatly appreciated.

Also, can anybody explain why on LS1046AFRWY board only [0,1,2,3] mappings are used for all nibbles?
Why there is no any [4,5,6,7]?

 

[valokuvaaja · Accepted solution]

@Bio_TICFSL 

I'm sorry, but your answer didn't help at all.

I was asking about which scheme of mappings I should choose and why.

UPDATE: we finally sorted it out, and we've got all DDR tests passed in CodeWarrior recently for our LS1046A custom board with 4GB + ECC memory (see screenshots).

Correct mapping is in the second listing. 

Mapping happens from the DDR controller point of view.

I provide correct mappings as example for the attached earlier screenshot to help new people who will be break their brains on this question:

LS1046        SDRAM
DDR_DQ00  ->  DQ1
DDR_DQ01  ->  DQ3
DDR_DQ02  ->  DQ2
DDR_DQ03  ->  DQ0
i.e. [1,3,2,0] 0x0C

LS1046        SDRAM
DDR_DQ04  ->  DQ5
DDR_DQ05  ->  DQ7
DDR_DQ06  ->  DQ6
DDR_DQ07  ->  DQ4
i.e. [5,7,6,4] 0x2C

LS1046        SDRAM
DDR_DQ08  ->  DQ9  (1)
DDR_DQ09  ->  DQ11 (3)
DDR_DQ10  ->  DQ10 (2)
DDR_DQ11  ->  DQ08 (0)
i.e. [1,3,2,0] 0x0C

LS1046        SDRAM
DDR_DQ12  ->  DQ13 (5)
DDR_DQ13  ->  DQ15 (7)
DDR_DQ14  ->  DQ14 (6)
DDR_DQ15  ->  DQ12 (4)
i.e. [5,7,6,4] 0x2C

Regarding to the question about mappings in LS1046AFRWY:

it turned out that [0,1,2,3] is eqiuivalent to [4,5,6,7].

[Bio_TICFSL]

Hello,

or discrete DDR4 parameters configuration, first you need to create a QCVS DDR Memory Controller Configuration  project with default configuration parameters, then modify parameters in Properties panel according to your DDR datasheet to generate the initial DDR controller configuration parameters, then use DDRv tool to connect to the target board to do validation, optimization and operational DDR test.

Please refer to https://community.nxp.com/docs/DOC-333349 

You could configure your target board as hard-coded RCW first, then do DDR validation with DDRv tool.

Regards