LS1046A - PCIe compliance mode - set speed to 5Gbit/s

[ferdinandgrossm]

Hello,

we're trying to do some PCIe compliance measurements for our customer on our custom CPU board.

The PCIe TX signals are connected to a differential probe with 50Ohm termination on our scope. When we power up the system we see what looks like the compliance pattern at 2.5Gbit/s.

I tried setting the PCI Express Link Control 2 Register (Link_Control_2_Register) at 0x036000A0 to 0x0012 in order to change the PCIe speed, but no change is visible on the scope.

Playing around with the other bits in the control register had no visible impact either.

I'm pretty sure I got the right PCIe controller; issuing a soft-reset using the PEX PFa Debug register (PEX_PF0_DBG) at 0x03680000 + 0x407FC turned off the pattern we saw. (And it turns out it is not possible to set the write enable and soft reset bits at the same time).

Also, when connecting a PCIe device we get the PCIe 2.0  5Gbit/s, so I'm sure our configuration supports the higher speed.

What am I missing? Is there another command I have to issue? Are there other registers I need to configure?

I'd appreciate any hints you could give me.

Thanks!

Regards

Ferdinand

[andrei_skok · Accepted solution]

When LS1046A is in RC mode and connected to the PCIE test fixture :
1. do a Read-Modified-Write configure write to PEX controller's Configure Space Link Control 2 Register. Please do not touch other bits except the following:
    a. Set the Target link speed bit field (T_LS) to the desired speed (0x2).
    b. Set the Enter Compliance (EC) bit
2) Our transmitter should be able to send out the desired compliance test pattern.

Have a great day,
Andrei

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[muaxi8]

i have the  same problem, Lx2080 can output only 2.5 Gbps,  but 5Gbps cannot be configured.

root@localhost:~# devmem

Usage: devmem { address } [ type [ data ] ]
address : memory address to act upon
type : access operation type : [b]yte, [h]alfword, [w]ord
data : data to be written

root@localhost:~#
root@localhost:~#
root@localhost:~# devmem 0x34000a0 h
/dev/mem opened.
Memory mapped at address 0xffffad6d4000.
Value at address 0x34000A0 (0xffffad6d40a0): 0x13
root@localhost:~#
root@localhost:~# devmem 0x34c07fc h
/dev/mem opened.
Memory mapped at address 0xffffabea5000.
Value at address 0x34C07FC (0xffffabea57fc): 0x3
root@localhost:~#
root@localhost:~#

[ferdinandgrossm]

Hello Andrei,

thanks, we got it working at 5Gbits/s.

Regards

Ferdinand

[masonyen]

Hi Ferdinand,

I met the same problem as yours. LS1046a PCIE only outputs at Gen1 2.5Gbits. How do you make LS1046a PCIE RC compliance mode runs at Gen2 and Gen3?

Cheers,

Mason