Hi everyone,
I have 11 devices attached to the SPI bus on the LS1046A. I wish there were more than 1 general purpose SPI core on this device (QSPI doesn't count), but we have to live within the constraints NXP gives us.
While it is possible to setup the device tree in Linux to specify additional chip selects as gpio, it appears the standard driver (spi-fsl-dspi.c) simply ignores the native CS limits of the hardware and assumes all chip selects are hardware no matter how things are configured. I have been trying to patch the kernel driver to behave more sanely in this regard, and have a couple of questions which I am hoping someone can answer:
1) Is there a non mainline driver for the SPI device on the LS1046A that is better than the fsl driver in the mainline kernel tree?
2) I am confused on exactly the SPI core operates in Extended SPI mode (MCR[XSPI] is set) . I want to do the following:
Assume the SPI (master mode) is idle with a native PCS line left asserted. A new transfer comes from the Linux controller, but for a device whose chipselect is on a GPIO line, therefore not controlled via the PUSHR register. Is it possible to de-assert the native PCS line without transmitting anything out the SPI bus? It is not clear to me from section 32 of the reference manual how this works. If I do a 16 bit write to bits 0-15 of the PUSHR register, will it execute this command immediately without waiting for a write to the TX_DATA FIFO? I.e. will it execute the command and not toggle any external clocks or data lines, so no external effects other than de-asserting the PCS lines?
Has anyone ever written a driver for this SPI core that handles this issue gracefully?
As always, appreciate the help on this forum.
