LS1046 LVPECL to LVDS for DIFF_SYSCLK

[nfj]

Hey,

  I unfortunately have to use a LVPECL clock generator for my application, and I'm trying to figure out how best to translate that to LVDS levels for the DIFF_SYSCLK/DIFF_SYSCLK_B inputs, which led me to some confusion.  After looking at the LS1046 datasheets, ref manual, and design checklist, as well as this post on the LS1021, I can't seem to figure out if I need to externally bias the inputs for the LS1046. The datasheet says that my CM voltage has to be between 50mV - 1570mV, but under Section 5.33, Figure 23 of the Design checklist, it shows only a two resistor network and no external bias.  

  What is the correct way to design for this? 

Thanks,

-Nate J

[mrudangshelat-13 · Accepted solution]

Hi @nfj 

The datasheet says the CM voltage range has to be between 50mV - 1570mV which means clock type, LVDS(fig.20 in AN5252) or HCSL (fig.21 in AN5252) will be accepted as an input. I suggest contacting the clock generator's vendor support team for the proper translation & termination value for LVPECL to LVDS or  LVPECL to HCSL.

Please consider the following link as reference: https://www.renesas.com/in/en/document/apn/lvpecl-hcsl-level-translation-and-termination?language=en

Regards,

Mrudang Shelat