LS1043ardb pbi related documents

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LS1043ardb pbi related documents

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zhoujianyun19
Contributor III

I debugging LS1043ardb development board .U-boot have ls1043ardb_pbi.cfg file ,Details are as follows:

#Configure Scratch register
09570600 00000000
09570604 10000000
#Alt base register
09570158 00001000
#Disable CCI barrier tranaction
09570178 0000e010
09180000 00000008
#USB PHY frequency sel
09570418 0000009e
0957041c 0000009e
09570420 0000009e
#flush PBI data
096100c0 000fffff

 

Please help provide PBI related documents.

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ufedor
NXP Employee
NXP Employee

16100c0 - refer to the LS1043A RM, Table 27-5. Description of PBL commands, Wait

1570178 - hidden CCI CONFIG register (additional information can be obtained by creating a Technical Case - refer to the https://community.freescale.com/thread/381898)

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ufedor
NXP Employee
NXP Employee

General description of the PBI commands is provided in the QorIQ LS1043A Reference Manual, Chapter 27 Pre-Boot Loader (PBL).

Please note that default PBL base address offset is 0x100_0000 and this offset is concatenated with 24-bit SYS_ADDR of a PBI command.

Decoding example:

09570600 00000000

ACS=0

BYTE_CNT=000100 (4 bytes)

CNT=1

SYS_ADDR=570600

Complete CCSR address with offset: 0x1570600 (SCFG_SCRATCHRW0)

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zhoujianyun19
Contributor III

Thank you request my problem.

I want to know PBI configure all  hardware resource.

I study ls1043ardb_pbi.cfg file.I don't find 0x16100c0  0x1570178  register declaration in LS1043A Reference Manual.

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ufedor
NXP Employee
NXP Employee

16100c0 - refer to the LS1043A RM, Table 27-5. Description of PBL commands, Wait

1570178 - hidden CCI CONFIG register (additional information can be obtained by creating a Technical Case - refer to the https://community.freescale.com/thread/381898)