LS1043a duart gibberish on serial0 when attempting to modify registers in serial1

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LS1043a duart gibberish on serial0 when attempting to modify registers in serial1

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endrunner_smw
Contributor III

I am able to console through Serial0 (0x21c0500) just fine in Uboot. However, when attempting to access registers to modify the baud rate for Serial1 (0x21c0600) something is not working correctly. If I attempt to boot the board after attempting to make changes to serial1 when booting completes I'll get a small burst gibberish on serial0 before the linux console log in prompt, it also interferes with how my serial should interact with an attached board. I thought that the two uarts were suppose to be independent of each other?

I need serial0 to be 115200 baud 8n1, and I need Serial1 to be 38400 baud 8n1 in Uboot. I'm able to access these fine from linux, but there is an additional layer of abstraction to make things easier there.

If I am reading registers correctly it looks like after a reboot Serial0 has 0xC1 in the Alternate function register which mentions having concurrent writes between uarts. Why is this set as default? It shouldn't be, right?

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endrunner_smw
Contributor III

Figured it out. The QorIQ LS1043A Reference Manual, Rev. 6, 7/2020 is incorrect. Diagram/Table 20.4.10.3 & 20.4.10.4 say that the DLAB is the least significant bit and the word length and stop bits are the most significant bits. This is reversed.

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endrunner_smw
Contributor III

Figured it out. The QorIQ LS1043A Reference Manual, Rev. 6, 7/2020 is incorrect. Diagram/Table 20.4.10.3 & 20.4.10.4 say that the DLAB is the least significant bit and the word length and stop bits are the most significant bits. This is reversed.

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endrunner_smw
Contributor III

Below is the memory dump of the uart registers for 0x21c0500 (serial0), and 0x21c0600 (serial1) in uboot where I need both serial connections.

=> md.b 0x21c0500 0x11
021c0500: 00 00 c1 03 03 00 11 00 00 00 00 00 00 00 00 00 ................
021c0510: 03 .
=> md.b 0x21c0600 0x11
021c0600: 00 00 01 00 00 60 11 00 00 00 00 00 00 00 00 00 .....`..........
021c0610: 01

Why does it appear that the Latch Access Bit is set in 0x21c0503 (Line Control Register)? Also in 0x21c0502 (alternate function register) why is concurrent write set? Do I need baud clock gated off or on if I need serial0 on 115200 and serial1 on 38400? The values also don't appear to match what is suppose to show coming out of reset. Serial0 appears to be in FIFO mode, not sure if that matters. While debugging if I switch particular registers then if I write to 0x21c0600 it'll show up on 0x21c0500, which is very wrong.

Where should I look for correcting this?

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