We have a LS1043ARDB connected to an FPGA via pcie. One of the memory spaces is a block of DDR memory.
I have a piece of standalone code that is linked towards the onboard system RAM, and also a seperate image that is linked to the pcie DDR memory.
The version that is linked to the system RAM works fine.
I can load the pcie-ddr bases image into the memory space, but I get a synchronous abort.
the error message gives a register dump, and and esr=0x8600000d
I know in ppc land, each memory space can be denied execution rights even if read/write access is allowed. I don't see anything that would drive that in the A53, but maybe I'm missing something?
1. I can acess the memory space via config and memory read/write commands from the u-boot command line.
2. I can fill and zero out the external memory. Statically, it behaves normally.
3. My test code just spins right now, it is not doing any I/o (yet)
We suspect that this may be due to the default Trustzone settings on the LS1043A.
Are there any application notes or other documentation on configuring these settings?
The manual describes the registers, but it's not a clear description on how they are used on the test board.
Using codewarrior, I can see that the u-boot is writing to the CSU config space and then once it gets to the command prompt, it has locked the CSU and blocked out the trustzone register space so I can't read it.
Without rebuilding the u-boot, is there a way for me to make it so that the u-boot code can't lock things down? If I lock the unit down before the u-boot code does, the values can't be changed until the boars is reset, according to the documentation. I am thinking I can halt the boot using codewarrior, Lock the CSU with benign values in it (allowing all access), I may be able to keep it from locking me out.
Is this the right forum for this question? I have not seen any responses.