LS1043A serdes protocol at 0x3455 ,how to modify?

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LS1043A serdes protocol at 0x3455 ,how to modify?

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huangtiandi
Contributor I

我将图片修改为0x3455后,可以在QSMGII Uboot中识别出来,但是四个端口的发送和接收异常,无法通信,并且进入系统也无法通信,我需要在哪里更改。

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bpe
NXP Employee
NXP Employee


You need a valid driver for your QSGMII PHY, a proper declaration of the PHY and it's connection to MDIO and SerDes in the Device Tree and initialization of the PHY management addresses in u-Boot if u-Boot needs any of your QSGMII links for  it's tasks.

For more information, see:

-- Ethernet PHY and MDIO binding specification:

https://source.codeaurora.org/external/qoriq/qoriq-components/linux/tree/Documentation/devicetree/bi...
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/tree/Documentation/devicetree/bi...

-- FMAN binding specification:

https://source.codeaurora.org/external/qoriq/qoriq-components/linux/tree/Documentation/devicetree/bi...

LS1043A-RDB board initialization code:

https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot/tree/board/freescale/ls1043ardb...

Device Tree source for LS1043A-RDB:

https://source.codeaurora.org/external/qoriq/qoriq-components/linux/tree/arch/arm64/boot/dts/freesca...

For the PHY driver availability and the Device Tree node properties required by the driver, consult at your PHY manufacturer.

Hope this helps
Platon

 

 

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huangtiandi
Contributor I

The software is configured to 0X1455 and the hardware SRDS_CLK is 125MHZ, QSGMII and XFI are both normal.    

The software is configured to 0X3455, and the hardware SRDS_CLK is 100MHZ. At this time, it can be recognized in QSMGII Uboot, but SGMII and SGMII are not normal,both of them can not be communicated.

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bpe
NXP Employee
NXP Employee

Google translation follows:

 

After I modified the picture to 0x3455, it can be recognized in QSMGII Uboot,
but the sending and receiving of the four ports are abnormal, and communication
is not possible, and the system cannot be communicated. Where do I need to change it.

 

 

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